MAX783C/D Просмотр технического описания (PDF) - Maxim Integrated

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MAX783C/D

Triple-Output Power-Supply Controller for Notebook Computers

Maxim Integrated 

Triple-Output Power-Supply Controller

for Notebook Computers

______________________________________________________________Pin Description

PIN

NAME

1

ON3

2

S—H—D—N–

3

D1

4

D2

5

VH

6

Q2

7

Q1

8

R—D—Y—5–

9

VPPA

10

VDD

11

VPPB

12

GND

13

REF

14

15-18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

SYNC

DA1, DA0,

DB1, DB0

ON5

SS5

CS5

DH5

LX5

BST5

DL5

PGND

FB5

VL

V+

DL3

BST3

LX3

DH3

FB3

CS3

SS3

FUNCTION

ON/O—F—F– control input to disable the +3.3V PWM. Tie directly to VL for automatic start-up.

Shutdown

shutdown.

cDonotnro'tlfionrpcuet,S—lHo—wD—-N–truheiglhoegricth. aTnieVtLo+VL0.f5oVr.automatic

start-up.

The 5V VL supply stays active in

#1 level-translator/comparator noninverting input, threshold = +1.650V. Controls Q1. Tie to GND if

unused.

#2 level-translator/comparator noninverting input (see D1).

External positive supply voltage input for the level translators/comparators and R—D—Y—5– output.

#2 level-translator/comparator output. Sources 20µA from VH when D2 is high. Sinks 500µA to GND when

D2 is low, even with VH = 0V.

#1 level translator/comparator output (see Q2).

Power-good indication for the main +5V supply. Low indicates greater than 4.5V at the +5V output.

Swings 0V to VH.

0V, 3.3V, 5V, 12V switchable PCMCIA VPP output. Sources 60mA. Controlled by DA0 and DA1.

+15V flyback input (feedback). A weak shunt regulator conducts 3mA to GND when VDD exceeds 19V.

VDD serves as the supply input for the VPP linear regulators.

0V, 3.3V, 5V, 12V switchable PCMCIA VPP output. Sources 60mA. Controlled by DB0 and DB1.

Low-current analog ground. Feedback reference point for all outputs.

3.3V reference output sources up to 5mA for external loads. Bypass to GND with 1µF/mA of load or

0.22µF minimum

Oscillator control/synchronization input. Connect to VL or GND for 200kHz; connect to REF for 300kHz.

For external clock synchronization in the 240kHz to 350kHz range, a high-to-low transition starts a new cycle.

PCMCIA digital control inputs with industry-standard coding (see Table 1).

ON/O—F—F– control input to disable the +5V PWM supply. Tie to VL for automatic start-up.

Soft-start control input for +5V. Ramp time to full current limit is 1ms/nF of capacitance to GND.

Current-sense input for +5V. Current limit level is +100mV referred to FB5.

Gate-drive output for the +5V high-side MOSFET.

Inductor connection for the +5V supply.

Boost capacitor connection for the +5V supply (0.1µF).

Gate-drive output for the +5V low-side MOSFET.

Power ground

Feedback and current-sense input for the +5V PWM.

5V logic supply voltage for internal circuitry. VL is always on and can source 5mA for external loads.

Supply voltage input from battery, 5.5V to 30V

Gate-drive output for the +3.3V low-side MOSFET.

Boost capacitor connection for the +3.3V supply (0.1µF).

Inductor connection for the +3.3V supply.

Gate-drive output for the +3.3V high-side MOSFET.

Feedback and current-sense input for the +3.3V PWM.

Current-sense input for +3.3V, current limit level is +100mV referred to FB3.

Soft-start input for +3.3V. Ramp time to full current limit is 1ms/nF of capacitance to GND.

_______________________________________________________________________________________ 7

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