MAX801 Просмотр технического описания (PDF) - Maxim Integrated

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MAX801

8-Pin µP Supervisory Circuits with ±1.5% Reset Accuracy

Maxim Integrated 

8-Pin µP Supervisory Circuits

with ±1.5% Reset Accuracy

VRST VLL

VCC

VLOWLINE

VRESET

tRP

VRESET

(MAX801)

tRP

VCE OUT

(MAX808)

VBATT

SHOWN FOR VCC = 0V to 5V, VBATT = 2.8V, CE IN = GND

Figure 2a. Timing Diagram, VCC Rising

VRST + VLR VRST

VCC

VLOWLINE

tLL

VRESET

tRD

VRESET

tRD

(MAX801)

VCE OUT

tRCE

(MAX808)

VBATT

SHOWN FOR VCC = 5V to 0V, VBATT = 2.8V, CE IN = GND

Figure 2b. Timing Diagram, VCC Falling

_______________Detailed Description

The MAX801/MAX808 microprocessor (µP) supervisory

circuits provide power-supply monitoring and backup-

battery switchover in µP systems. The MAX801 also

provides program-execution watchdog functions

(Figure 1). Use of BiCMOS technology results in an

improved, 1.5% reset-threshold precision while keeping

supply currents typically at 68µA (48µA for the

MAX808). The MAX801/MAX808 are intended for bat-

tery-powered applications that require high reset-

threshold precision, allowing a wide power-supply

operating range while preventing the system from oper-

ating below its specified voltage range.

RESET and RESET Outputs

The MAX801/MAX808’s RESET output ensures that the

µP powers up in a known state, and prevents code-

execution errors during power-down and brownout

conditions. It does this by resetting the µP, terminating

program execution when VCC dips below the reset

threshold. Each time RESET is asserted, it stays low for

at least the 200ms reset timeout period (set by an inter-

nal timer) to ensure the µP has adequate time to return

to an initial state. The internal timer restarts any time

VCC goes below the reset threshold (VRST) before the

reset timeout period is completed. The watchdog timer

on the MAX801 can also initiate a reset (see the

MAX801 Watchdog Timer section).

The RESET output is active low, and is implemented with

a strong pull-down/relatively weak pull-up structure. It is

guaranteed to be a logic low for 0V < VCC < VRST, pro-

vided VBATT is greater than 2V. Without a backup bat-

tery, RESET is guaranteed valid for VCC ≥ 1V.

The RESET output is the inverse of the RESET output; it

both sources and sinks current and cannot be wire-OR

connected.

Low-Line Comparator

The low-line comparator monitors VCC with a threshold

voltage typically 52mV above the reset threshold, with

13mV of hysteresis. Use LOWLINE to provide a non-

maskable interrupt (NMI) to the µP when power begins

to fall, initiating an orderly software shutdown routine. In

most battery-operated portable systems, reserve ener-

gy in the battery provides ample time to complete the

shutdown routine once the low-line warning is encoun-

tered and before reset asserts. If the system must con-

tend with a more rapid VCC fall time (such as when the

main battery is disconnected, when a DC-DC converter

shuts down, or when a high-side switch is opened dur-

ing normal operation), use capacitance on the VCC line

to provide time to execute the shutdown routine (Figure

3). First calculate the worst-case time required for the

system to perform its shutdown routine. Then, with

worst-case shutdown time, worst-case load current,

and minimum low-line to reset threshold (VLR(min)),

8 _______________________________________________________________________________________

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