MAX6862UK225(2004) Просмотр технического описания (PDF) - Maxim Integrated

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MAX6862UK225
(Rev.:2004)

Nanopower µP Supervisory Circuits with Manual Reset and Watchdog Timer

Maxim Integrated 

Nanopower µP Supervisory Circuits with

Manual Reset and Watchdog Timer

ABSOLUTE MAXIMUM RATINGS

VCC, Open-Drain RESET to GND ..........................-0.3V to +6.0V

MR, Push-Pull RESET, RESET,

WDI, CT, I.C............................................-0.3V to (VCC + 0.3V)

Input Current, Output Current (all pins)............................±20mA

Continuous Power Dissipation (TA = +70°C)

5-Pin SOT23 (derate 7.1mW/°C above +70°C)............571mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature .....................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(VCC = 1.2V to 5.5V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 2.5V, TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP MAX UNITS

Supply Voltage

Supply Current

VCC

TA ≥ 0°C

1.1

TA = -40°C to +85°C

1.2

VCC > VTH, no load, VCC = 5.0V

ICC

reset output

VCC = 3.3V

deasserted (Note 2) VCC = 1.8V

VCC < VTH, no load, reset output asserted

5.5

V

5.5

210

400

190

380

nA

170

370

7

15

µA

VCC Reset Threshold

VTH

VCC falling (see Table 2)

VTH -

2.5%

VTH

VTH +

2.5%

V

Reset Threshold Hysteresis

Reset Timeout Period

VHYST

tRP

Reset asserted to reset deasserted

D1

D2

VCC = VTH + 150mV D3

(Figures 2 and 3)

D4

D5

D6

10

40

150

1200

300

600

0.5

15

60

225

1800

450

900

25

80

300

2400

600

1200

%VTH

ms

VCC to Reset Delay

tRD

VCC falling from (VTH + 100mV) to

(VTH - 100mV) at 10mV/µs

VCC ≥ 1.1V, ISINK = 50µA,

RESET asserted, TA ≥ 0°C

VOL

VCC ≥ 1.2V, ISINK = 100µA,

RESET asserted

40

µs

0.3

0.3

RESET Output Voltage

VCC ≥ 2.12V, ISINK = 1.2mA,

RESET asserted

0.3

V

VCC ≥ 1.71V, ISOURCE = 200µA,

RESET deasserted, push-pull RESET only

0.8 x VCC

VOH

VCC ≥ 2.38V, ISOURCE = 500µA,

RESET deasserted, push-pull RESET only

0.8 x VCC

Open-Drain RESET Leakage

Current

ILKG RESET deasserted

25

nA

2 _______________________________________________________________________________________

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