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MAX686

DAC-Controlled Boost/Inverter LCD Bias Supply with Internal Switch

Maxim Integrated 

DAC-Controlled Boost/Inverter

LCD Bias Supply with Internal Switch

Power-OK Comparator

POK is the input to the power-OK comparator. The

comparator drives an internal N-channel MOSFET. The

MOSFET’s open-drain output, LCDON, can drive an

external PNP transistor or P-channel MOSFET, switch-

ing a positive VOUT to the LCD (Figures 6 and 7). When

the voltage at POK exceeds 1.125V (power OK),

LCDON goes low, turning on the external PNP transis-

tor. When the voltage at POK drops below 1.125V

(power not OK), the external PNP transistor turns off,

cutting off power to the LCD display. This feature

ensures that the LCD display is not damaged due to

improper voltage levels. During shutdown or undervolt-

age lockout, LCDON is high impedance.

Shutdown Mode

When SHDN is low, the MAX686 enters shutdown

mode, in which the control circuit, POK comparator,

DAC output buffer, reference, and internal biasing cir-

cuitry turn off. The DAC setting is stored as long as VCC

remains above the DAC reset threshold. Supply current

drops to 1.5µA. SHDN is a logic-level input; connect it

to VCC for normal operation.

The output voltage in shutdown mode depends on the

output voltage polarity. In the positive output voltage

configuration (Figure 1), the output is directly connect-

ed to the input through the diode (D1) and the inductor

(L1). When the device is in shutdown mode, the output

voltage falls to one diode drop below the input voltage,

and any load connected to the output may still conduct

current. In the negative output voltage configuration

(Figures 2 and 3), there is no DC path between the

input and the output, and the output falls to GND in

shutdown mode.

Internal DAC

The MAX686 contains an internal 6-bit counter and

DAC to control the output voltage digitally (see the sec-

tion Setting the Output Voltage with the DAC). The UP

and DN input pins drive an internal up/down counter

that directly controls the DAC. To increase the magni-

tude of VOUT in the boost configuration, apply a rising

edge to UP. This decreases the DAC output voltage

one step and correspondingly increases VOUT.

Conversely, to decrease the magnitude of VOUT, apply

a rising edge to DN. This increases the DAC output

voltage one step and correspondingly decreases

VOUT. The UP and DN control direction reverses for a

negative output to maintain the same control direction of

the absolute magnitude of the output voltage. Upon

power-up, the DAC code internally goes to mid-scale.

The DAC’s internal counter does not roll over once it

reaches full scale or zero. Therefore, additional rising

edges to make the counter roll over are ignored, pre-

venting unexpected undervoltages or overvoltages.

Internal Reference

The MAX626’s 1.25V internal reference is accurate to

±2% over temperature. It can source up to 50µA of cur-

rent and should be bypassed with at least a 0.1µF

capacitor. See the Bypass Capacitors section.

Design Procedure

Setting the Output Voltage with the DAC

For either positive or negative output voltage applica-

tions, set the MAX686’s output voltage using three exter-

nal resistors (R1, R2, and R3) as shown in Figures 1, 2,

and 3. Since the input bias current at FB has a 50nA

maximum value, large resistors can be used in the

feedback loop without a significant loss of accuracy.

Select R1 to be in the 10kΩ to 220kΩ range and calcu-

late R2 and R3 using the applicable equations from the

following subsections.

Setting the Minimum Positive Output Voltage

The minimum output voltage is set with the resistor-

divider (R1-R2, Figure 1) from VOUT to FB. The mini-

mum output voltage occurs when VDACOUT = VFB =

1.25V. Therefore, R3 has no effect on the minimum out-

put voltage. Choose R1 to be 120kΩ so that the current

in the divider is about 10µA. Then determine R2 as fol-

lows:

R2 = R1 x (VOUT(MIN) - VFB) / VFB

For example, if VOUT(MIN) = 12.5V:

R2 = 120kΩ x (12.5 - 1.25) / (1.25) =1.08MΩ

Mount R1 and R2 close to the FB pin to minimize para-

sitic capacitance.

Setting the Maximum Positive Output Voltage

The DAC is adjustable from 0V to 1.25V in 64 steps,

and 1LSB = 1.25V / 63 = 19.8mV. Calculate R3 to

adjust VOUT with DACOUT (Figure 1).

For VOUT(MAX) = 25V and VOUT(MIN) = 12.5V, deter-

mine R3 as follows:

R3 = R2 x (VFB) / (VOUT(MAX) - VOUT(MIN))

= 1.08MΩ x (1.25) / (25 - 12.5) = 108kΩ

The general form for VOUT as a function of the DAC out-

put (VDACOUT) is:

VOUT = VOUT(MIN) + (VFB - VDACOUT) x R2 / R3

At power-up, the DAC resets to mid-scale where

VDACOUT = 0.635V. Therefore, the output voltage after

power-up is:

VOUT(MID) = VOUT(MIN) + (1.25 - 0.635) x

R2 / R3 = 18.65V

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