MAX6720A(2019) Просмотр технического описания (PDF) - Maxim Integrated

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MAX6720A
(Rev.:2019)

Dual/Triple, Ultra-Low-Voltage, SOT23 μP Supervisory Circuits

Maxim Integrated 

MAX6715A–MAX6729A/

MAX6797A

Dual/Triple, Ultra-Low-Voltage, SOT23 μP

Supervisory Circuits

Absolute Maximum Ratings

Terminal Voltage (with respect to GND)

VCC1, VCC2..........................................................-0.3V to +6V

Open-Drain RST, RST1, RST2, PFO, RST.............-0.3V to +6V

Continuous Power Dissipation (TA = +70°C)

5-Pin SOT23-5 (derate 3.9mW/°C above +70°C).....312.6mW

6-Pin SOT23-6 (derate 8.7mW/°C above +70°C)........696mW

Push-Pull RST, RST1, PFO, RST........... -0.3V to (VCC1 + 0.3V)

Push-Pull RST2...................................... -0.3V to (VCC2 + 0.3V)

RSTIN, PFI, MR, WDI..............................................-0.3V to +6V

8-Pin SOT23-8 (derate 5.6mW/°C above +70°C).....444.4mW

Operating Temperature Range......................... -40°C to +125°C

Storage Temperature Range............................. -65°C to +150°C

Input Current/Output Current (all pins)...............................20mA

Junction Temperature......................................................+150°C

Lead Temperature (soldering, 10s)..................................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Package Information

5 SOT23

PACKAGE CODE

U5+1

Outline Number

21-0057

Land Pattern Number

90-0174

Thermal Resistance, Four-Layer Board:

Junction to Ambient (θJA)

Junction to Case (θJC)

Thermal Resistance, Multilayer Board:

324.3°C/W

82°C/W

Junction to Ambient (θJA)

Junction to Case (θJC)

255.9°C/W

81°C/W

6 SOT23

PACKAGE CODE

U6+1/U6+1A

Outline Number

21-0058

Land Pattern Number

90-0175

Thermal Resistance, Four-Layer Board:

Junction to Ambient (θJA)

Junction to Case (θJC)

Thermal Resistance, Multilayer Board:

N/A

80°C/W

Junction to Ambient (θJA)

Junction to Case (θJC)

115°C/W

80°C/W

8 SOT23

PACKAGE CODE

K8SN+1

Outline Number

21-0078

Land Pattern Number

90-0176

Thermal Resistance, Four-Layer Board:

Junction to Ambient (θJA)

Junction to Case (θJC)

Thermal Resistance, Multilayer Board:

N/A

80°C/W

Junction to Ambient (θJA)

Junction to Case (θJC)

180°C/W

60°C/W

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package

code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on

package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

www.maximintegrated.com

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