MAX6304ESA Просмотр технического описания (PDF) - Maxim Integrated

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MAX6304ESA

+5V / Low-Power uP Supervisory Circuits with Adjustable Reset/Watchdog

Maxim Integrated 

+5V, Low-Power µP Supervisory Circuits

with Adjustable Reset/Watchdog

VCC

MAX6303

VCC

0.1µF

RESET

GND

100kΩ

MAX6304

VCC

RESET

VCC

100kΩ

0.1µF

GND

Figure 9. Ensuring RESET Valid to VCC = 0V

In those applications where RESET must be valid down

to 0V, adding a pulldown resistor between RESET and

ground sinks any stray leakage currents, holding

RESET low (Figure 9). The value of the pulldown resistor

is not critical; 100kΩ is large enough not to load RESET

and small enough to pull RESET to ground. For applica-

tions using the MAX6304, a 100kΩ pullup resistor

between RESET and VCC will hold RESET high when

VCC falls below 1V (Figure 10).

Watchdog-Software Considerations

To help the watchdog timer monitor software execution

more closely, set and reset the watchdog input at differ-

ent points in the program, rather than pulsing the

watchdog input high-low-high or low-high-low. This

technique avoids a stuck loop in which the watchdog

timer would continue to be reset within the loop, keeping

the watchdog from timing out.

Figure 11 shows an example of a flow diagram where

the I/O driving the watchdog input is set high at the

beginning of the program, set low at the beginning of

every subroutine or loop, then set high again when the

program returns to the beginning. If the program should

hang in any subroutine the problem would quickly be

corrected, since the I/O is continually set low and the

watchdog timer is allowed to time out, causing a reset

or interrupt to be issued. When using extended mode,

as described in the Watchdog Input Current section,

this scheme does result in higher average WDI input

current than does the method of leaving WDI low for the

majority of the timeout period and periodically pulsing it

low-high-low.

Layout Considerations

SRT and SWT are precision current sources. When

developing the layout for the application, be careful to

minimize board capacitance and leakage currents

around these pins. Traces connected to these pins

Figure 10. Ensuring RESET Valid to VCC = 0V

START

SET WDI

LOW

SUBROUTINE OR

PROGRAM LOOP

SET WDI HIGH

RETURN

END

Figure 11. Watchdog Flow Diagram

should be kept as short as possible. Traces carrying

high-speed digital signals and traces with large voltage

potentials should be routed as far from these pins as

possible. Leakage currents and stray capacitance

(e.g., a scope probe) at these pins could cause errors

in the reset and/or watchdog timeout period. When

evaluating these parts, use clean prototype boards to

ensure accurate reset and watchdog timeout periods.

RESET IN is a high-impedance input that is typically

driven by a high-impedance resistor-divider network

(e.g., 1MΩ to 10MΩ). Minimize coupling to transient sig-

nals by keeping the connections to this input short. Any

DC leakage current at RESET IN (e.g., a scope probe)

causes errors in the programmed reset threshold. Note

that sensitive pins are located on the GND side of the

device, away from the digital I/O, to simplify board layout.

10 ______________________________________________________________________________________

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