MAX550BCPA Просмотр технического описания (PDF) - Maxim Integrated

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MAX550BCPA

Low-Power, +2.5V to +5.5V, 8-Bit Voltage-Output DAC in µMAX

Maxim Integrated 

Low-Power, +2.5V to +5.5V, 8-Bit

Voltage-Output DAC in µMAX

CS

SCLK

DIN

tCSH0

tCSS0

tCH

tDS

tCL

tDH

tCSW

tCSH1

tCSS1

Figure 3. Detailed Serial-Interface Timing Diagram

Table 1. Control-Byte/Input-Word Bit

Definitions

UB1* X Unassigned Bit 1

UB2

X Unassigned Bit 2

UB3

X Unassigned Bit 3

C2

0 Power-Up Mode

C2

1 Power-Down Mode

C1

Control

Byte

C1

0

DAC Register Load Operation

Disabled

1

DAC Register Load Operation

Enabled

C0

0

DAC Output Updated on Rising

Edge of CS

C0

1 Unassigned Operation

AB1

0 Assigned Bit 1

AB2

1 Assigned Bit 2

D7

X DAC Data Bit 7 (MSB)

D6

X DAC Data Bit 6

D5

X DAC Data Bit 5

Data D4

Byte D3

X DAC Data Bit 4

X DAC Data Bit 3

D2

X DAC Data Bit 2

D1

X DAC Data Bit 1

D0** X DAC Data Bit 0 (LSB)

X = Don’t care

*Clocked in first

**Clocked in last

Microprocessor Interfacing

The MAX550B serial interface is compatible with

Microwire, SPI, and QSPI interface standards. For SPI,

clear the CPOL and CPHA bits (CPOL = 0 and

CPHA = 0). CPOL = 0 sets the idle clock state to zero

and CPHA = 0 changes data at SCLK’s falling edge.

This setting allows SPI to run at full clock speeds

(1.5MHz). If a serial port is not available on your µP,

three bits of a parallel port can be used to emulate a

serial port by bit manipulation. Minimize digital

feedthrough at the DAC output by operating the serial

clock only when necessary.

––––––––––––––Applications Information

Power-Supply

and Ground Considerations

Connect GND to the highest-quality ground available.

Bypass VDD with a 0.1µF to 0.22µF capacitor to GND.

The reference input can be used without bypassing.

However, for optimum line/load-transient response and

noise performance, bypass the reference input with a

0.1µF to 4.7µF capacitor to GND.

Careful PC board layout minimizes crosstalk between

the DAC output, the reference, and the digital inputs.

Separate analog traces by running ground traces

between them. Make sure high-frequency digital lines

are not routed parallel to analog lines.

8 _______________________________________________________________________________________

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