MAX5812 Просмотр технического описания (PDF) - Maxim Integrated

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MAX5812

12-Bit Low-Power, 2-Wire, Serial Voltage-Output DAC

Maxim Integrated 

12-Bit Low-Power, 2-Wire, Serial

Voltage-Output DAC

SDA

SCL

tHD, STA

tSU, DAT

tLOW

tHIGH

tHD, DAT

tR

tF

tSU, STA

tHD, STA

tBUF

tSP

tSU, STO

START CONDITION

REPEATED START CONDITION

STOP

CONDITION

Figure 1. Two-Wire Serial lnterface Timing Diagram

and a serial clock line (SCL). The MAX5812 is SMBus

S

Sr

compatible within the range of VDD = 2.7V to 3.6V. SDA

SCL

and SCL facilitate bidirectional communication between

the MAX5812 and the master at rates up to 400kHz.

Figure 1 shows the 2-wire interface timing diagram. The

MAX5812 is a transmit/receive slave-only device, rely-

SDA

ing upon a master to generate a clock signal. The mas-

ter, typically a microcontroller, initiates data transfer on

the bus and generates SCL to permit that transfer.

A master device communicates to the MAX5812 by

transmitting the proper address followed by command

and/or data words. Each transmit sequence is framed

by a START (S) or REPEATED START (Sr) condition and

a STOP (P) condition. Each word transmitted over the

bus is 8 bits long and is always followed by an

acknowledge clock pulse.

The MAX5812 SDA and SCL drivers are open-drain out-

puts, requiring a pullup resistor (500Ω or greater) to

generate a logic high voltage (see the Typical Operating

Circuit). Series resistors RS are optional. These series

resistors protect the input stages of the MAX5812 from

high-voltage spikes on the bus lines and minimize

crosstalk and undershoot of the bus signals.

Figure 2. START/STOP Conditions

SCL

SDA

STOP

START

LEGAL STOP CONDITION

SCL

SDA

Bit Transfer

One data bit is transferred during each SCL clock

cycle. The data on SDA must remain stable during the

high period of the SCL clock pulse. Changes in SDA

while the SCL is high are control signals (see the

START and STOP Conditions section). SDA and SCL

idle high when the I2C bus is not busy.

START

ILLEGAL

STOP

ILLEGAL EARLY STOP CONDITION

Figure 3. Early STOP condition

START and STOP Conditions

When the serial interface is inactive, SDA and SCL idle

high. A master device initiates communication by issu-

ing a START condition. A START condition is a high-to-

START

CONDITION

P

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