MAX550AC Просмотр технического описания (PDF) - Maxim Integrated

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MAX550AC

+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in µMAX Package

Maxim Integrated 

+2.5V to +5.5V, Low-Power, Single/Dual,

8-Bit Voltage-Output DACs in µMAX Package

edge on CS programs the DAC. The input registers can

be loaded independently or simultaneously without

updating the DAC registers. This allows both DAC reg-

isters to be updated simultaneously with different digital

values. The DAC outputs reflect the data stored in the

DAC registers. LDAC can be used to asynchronously

update the DAC registers independently of CS

(MAX548A/MAX550A). With C1 set high, setting C0 in

the control word forces the DAC register(s) to be

updated on LDAC’s falling edge, rather than CS’s rising

edge (Table 1).

Initialization

The MAX548A/MAX549A/MAX550A have an internal

power-on reset. At power-up, all internal registers are

reset to zero; therefore, an initialization write sequence

is not necessary.

Serial-Input Data Format and Control Codes

The control byte determines which input registers/DAC

registers are updated (Table 1). The DAC input regis-

ters are updated on the rising edge of CS. The DAC

registers can be updated on CS’s rising edge or on

LDAC’s falling edge after CS goes high. Bit C0 of the

control byte determines how the DAC registers are

updated for the MAX548A/MAX550A. The MAX549A

has no LDAC pin; the DAC registers are always up-

dated on CS’s rising edge (C0 in the control byte has

no effect).

Tables 2, 3, and 4 list the serial-input command format

for the MAX548A, MAX549A, and MAX550A, respec-

tively. The 16-bit input word consists of an 8-bit control

byte and an 8-bit data byte. The control byte is not

decoded internally. Every control bit performs one

Table 1. Control-Byte/Input-Word Bit Definitions

BIT NAME

STATE

OPERATION

UB1*

X

UB2

X

UB3

X

C2

0

C2

1

C1

0

CONTROL BYTE

C1

1

C0

0

C0

1

A1

0

A1

1

A0

0

A0

1

D7

—

D6

—

D5

—

DATA

BYTE

D4

—

D3

—

D2

—

D1

—

D0**

—

X = Don’t care *Clocked in first **Clocked in last

Unassigned Bit 1

Unassigned Bit 2

Unassigned Bit 3

Power-Up Mode

Power-Down Mode

DAC Register Load Operation Disabled

DAC Register Load Operation Enabled

DAC Register Updated on CS’s Rising Edge

DAC Register Updated on LDAC’s Falling Edge (MAX549A = Don’t Care)

Do Not Address DAC B (MAX550A = Don’t Care)

Address DAC B (MAX550A = Don’t Care)

Do Not Address DAC A

Address DAC A

DAC Data Bit 7 (MSB)

DAC Data Bit 6

DAC Data Bit 5

DAC Data Bit 4

DAC Data Bit 3

DAC Data Bit 2

DAC Data Bit 1

DAC Data Bit 0 (LSB)

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