MAX550AC Просмотр технического описания (PDF) - Maxim Integrated

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MAX550AC

+2.5V to +5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in µMAX Package

Maxim Integrated 

+2.5V to +5.5V, Low-Power, Single/Dual,

8-Bit Voltage-Output DACs in µMAX Package

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +2.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

DYNAMIC PERFORMANCE

Digital Feedthrough and

Crosstalk

CS = high, all digital inputs from 0V to VDD

50

nV-sec

Voltage-Output Settling Time

Voltage-Output Slew Rate

Wake-Up Time at Power-Up

POWER SUPPLIES

Supply Voltage Range

To ±1/2LSB, CL = 20pF

CL = 20pF

VDD = 2.5V

VDD = 5.5V

CL = 20pF

VDD

Outputs unloaded, all inputs = GND or VDD

4

µs

1.4

V/µs

3.1

4

µs

2.5

5.5

V

Supply Current (MAX548A)

Outputs unloaded,

VDD = 5.5V

IDD

all inputs = GND or

VDD (Note 5)

VDD = 2.5V

330

550

µA

150

250

Supply Current

(MAX549A/MAX550A)

Shutdown Current

IDD

Outputs unloaded, all inputs = GND or VDD;

VDD = 5.5V

Shutdown mode

0.3

10

µA

0.3

µA

TIMING CHARACTERISTICS

(VDD = +2.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Digital inputs switching from 0V to VDD.) (Figure 3) (Note 4)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

SCLK Pulse Width High

tCH

40

ns

SCLK Pulse Width Low

tCL

40

ns

DIN to SCLK High Setup

tDS

30

ns

DIN to SCLK High Hold

tDH

VDD = 2.5V

VDD = 5.5V

0

ns

10

CS Low to SCLK High Setup

tCSS0

30

ns

CS High to SCLK High Setup

tCSS1

30

ns

SCLK High to CS Low Hold

tCSH0

10

ns

Delay, SCLK High to CS High

tCSH1

VDD = 2.5V

VDD = 5.5V

10

ns

20

CS Pulse Width High

tCSW

40

ns

SCLK Period

tCP

80

ns

LDAC Pulse Width Low

tLDAC

MAX548A/MAX550A only

50

ns

CS High to LDAC Low

tCSLD

MAX548A/MAX550A only

50

ns

VDD High to CS Low

5

µs

Note 1: Cold temperature specifications (to -40°C) guaranteed by design using six sigma design limits.

Note 2: Worst-case input resistance at REF occurs at DAC code 55 hex.

Note 3: Worst-case reference input current occurs at DAC code 55 hex.

Note 4: Guaranteed by design. Not production tested.

Note 5: IDD measured with DACs loaded with worst-case DAC code 55 hex.

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