MAX5134 Просмотр технического описания (PDF) - Maxim Integrated

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MAX5134

Pin-/Software-Compatible, 16-/12-Bit, Voltage-Output DACs

Maxim Integrated 

Pin-/Software-Compatible,

16-/12-Bit, Voltage-Output DACs

when using the internal reference. Bypass REFO to

GND with a 47pF (maximum 100pF) capacitor.

Alternatively, if heavier decoupling is required, use a

1kΩ resistor in series with a 1µF capacitor in parallel

with the existing 100pF capacitor. REFO can deliver up

to 100µA of current with no degradation in perfor-

mance. Configure other reference voltages by applying

a resistive potential divider with a total resistance

greater than 33kΩ from REFO to GND.

External Reference

The external reference input features a typical input

impedance of 113kΩ and accepts an input voltage

from +2V to AVDD. Connect an external voltage

supply between REFI and GND to apply an ex-

ternal reference. Leave REFO unconnected. Visit

www.maxim-ic.com/products/references for a list of

available external voltage-reference devices.

AVDD as Reference

Connect AVDD to REFI to use AVDD as the reference

voltage. Leave REFO unconnected.

Serial Interface

The MAX5134–MAX5137 3-wire serial interface is com-

patible with MICROWIRE, SPI, QSPI, and DSPs (Figures

2, 3). The interface provides three inputs, SCLK, CS,

and DIN and one output, READY. Use READY to verify

communication or to daisy-chain multiple devices (see

the READY section). READY is capable of driving a

20pF load with a 30ns (max) delay from the falling edge

of SCLK. The chip-select input (CS) frames the serial

data loading at DIN. Following a chip-select input’s

high-to-low transition, the data is shifted synchronously

and latched into the input register on each falling edge

of the serial-clock input (SCLK). Each serial word is 24

bits. The first 8 bits are the control word followed by 16

data bits (MSB first), as shown in Table 1. The serial

input register transfers its contents to the input registers

after loading 24 bits of data. To initiate a new data

transfer, drive CS high, keep CS high for a minimum of

33ns before the next write sequence. The SCLK can be

either high or low between CS write pulses. Figure 1

shows the timing diagram for the complete 3-wire serial-

interface transmission.

Table 1. Operating Mode Truth Table*

CONTROL BITS

MSB

C7 C6 C5 C4 C3 C2 C1

0000 0 0 0

24-BIT WORD

DATA BITS

C0 D15 D14 D13 D12 D11 D10 D9 D8

0 X XXX X X X X

DESC

LSB

FUNCTION

D7 D6–D0

X

X NOP No operation.

0000 0

0

0

1

X

X

X

X

DAC DAC DAC DAC

3210

X

Move contents of input

to DAC registers

X LDAC indicated by 1’s. No

effect on registers

indicated by 0’s.

0000 0 0 1 0 X X X X X X X X

X

X CLR Software clear.

Power down DACs

0000 0 0

1

1 X X X X DAC DAC DAC DAC READY_EN X

3210

Power indicated by 1’s.

Control Set READY_EN = 1 to

enable READY.

0 0 0 0 0 1 0 1 0 0 0 0 0 0 LIN 0

0

0 Linearity Optimize DAC linearity.

0

0

0

1

DAC

3

DAC

2

DAC

1

DAC

0

D15

D14 D13 D12

D11

D10

D9

D8

D7

Write to selected input

D6 Write registers (DAC output

not affected).

0 0 1 1 DAC DAC DAC DAC D15 D14 D13 D12 D11 D10 D9 D8

D7

321 0

0010 0 0 0 0 X X X X X X X X

X

Write to selected input

D6

Write- and DAC registers,

through DAC outputs updated

(writethrough).

X NOP No operation.

*For the MAX5136/MAX5137, DAC2 and DAC3 do not exist. For the MAX5135/MAX5137, D0–D3 are don’t-care bits.

10 ______________________________________________________________________________________

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