MAX498 Просмотр технического описания (PDF) - Maxim Integrated
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MAX498 Datasheet PDF : 16 Pages
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Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
______________________________________________________________Pin Description
PIN
MAX498
1, 3, 5,
11, 13,
19
2
MAX499
2, 4, 9,
11, 24
1
4
3
6
5
NAME
GND
IN1A
IN2A
IN3A
7, 22
6, 18
VCC
8
—
IN0B
9, 21
7, 17
VEE
10
12
14
15, 17
16
18
20
23
8
10
12
13, 15
14
16
19
—
IN1B
IN2B
IN3B
N.C.
OUT3
OUT2
OUT1
OUT0
24
20
CS
25
21
A0
26
22
EN
27
23
LE
28
—
IN0A
FUNCTION
Analog Ground. All ground pins are internally connected. Connect all ground pins externally to
ground to minimize impedance.
Signal Input 1, Channel A
Signal Input 2, Channel A
Signal Input 3, Channel A
Positive Power-Supply Voltage. Connect VCC to +5V. VCC pins are internally connected.
Connect both pins externally to +5V to minimize supply impedance. Bypass each pin to
ground with a 0.1µF ceramic capacitor.
Signal Input 0, Channel B
Negative Power-Supply Voltage. Connect VEE to -5V. VEE pins are internally connected.
Connect both pins to -5V externally to minimize supply impedance. Bypass each pin to
ground with a 0.1µF ceramic capacitor.
Signal Input 1, Channel B
Signal Input 2, Channel B
Signal Input 3, Channel B
No Connect. Not internally connected; connect to GND.
Output 3
Output 2
Output 1
Output 0
Chip-Select Input. When CS is low, the A0 and EN latches are transparent. The data present at A0
is latched when CS goes high. LE’s status determines whether EN is latched along with A0, or if the
EN latch remains transparent independently of CS.
Address Input. A0 = 0 selects channel A, and A0 = 1 selects channel B if CS is low. A0 is
latched on CS’s low-to-high transition.
Output Buffer-Enable Input. EN = 0 enables the output buffer amplifiers, and EN = 1 disables
the output buffers if CS is low. EN is latched during CS’s low-to-high transition if LE is high. EN
is not latched if LE is low.
Latch-Enable Input. With LE = 1, EN is latched along with A0 when CS goes high. When LE = 0,
the EN latch is transparent independently of CS’s state.
Signal Input 0, Channel A
_______________________________________________________________________________________ 7
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