MAX4358ECE Просмотр технического описания (PDF) - Maxim Integrated

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MAX4358ECE

32 x 16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers

Maxim Integrated 

32 x 16 Nonblocking Video Crosspoint Switch

with On-Screen Display Insertion and I/O Buffers

SWITCHING CHARACTERISTICS

((VCC - VEE) = +4.5V to +10.5V, VDD = +2.7V to +5.5V, DGND = AGND = 0, VIN_ = VOSDFILL_ = 0 for dual supplies, VIN_ =

VOSDFILL_ = +1.75V for single supply, RL = 150Ω to AGND, CL = 100pF, AV = +1V/V, and TA = TMIN - TMAX, unless otherwise noted.

Typical values are at TA = +25°C. )

PARAMETER

Delay: UPDATE to Video Out

Delay: UPDATE to AOUT

SYMBOL

tPdUdVo

tPdUdAo

CONDITIONS

VIN = 0.5V step

MODE = 0, time to AOUT = low after

UPDATE = low

MIN TYP MAX UNITS

200

450

ns

30

200

ns

Delay: OSDKEY_ to Output

Delay: SCLK to DOUT Valid

Delay: Output Disable

Delay: Output Enable

Setup: CE to SCLK

Setup: DIN to SCLK

Hold Time: SCLK to DIN

Minimum High Time: SCLK

Minimum Low Time: SCLK

Minimum Low Time: UPDATE

Setup Time: UPDATE to SCLK

tPdOkVo/

tPdOfVo

tPdDo

tPdHOeVo

tPdLOeVo

tSuCe

tSuDi

tHdDi

tMnHCk

tMnLCk

tMnLUd

tSuHUd

VOUT = 0.5V step

VDD = +5V

VDD = +3V

Logic state change in DOUT on active

SCLK edge

VOUT = 0.5V, 1kΩ pulldown to AGND

Output disabled, 1kΩ pulldown to AGND,

VIN = 0.5V

Rising edge of UPDATE to falling edge of

SCLK

40

ns

60

30

200

ns

300

800

ns

200

800

ns

100

ns

100

ns

100

ns

100

ns

100

ns

100

ns

100

ns

Hold Time: SCLK to UPDATE

tHdHUd

Falling edge of SCLK to falling edge of

UPDATE

100

ns

Setup Time: MODE to SCLK

tSuMd

Minimum time from clock edge to MODE

with valid data clocking

100

ns

Hold Time: MODE to SCLK

Minimum Low Time: RESET

Delay: RESET

tHdMd

Minimum time from clock edge to MODE

with valid data clocking

100

tMnLRst

tPdRst

10kΩ pulldown to AGND

ns

300

ns

600

ns

Note 1: Associated output voltage may be determined by multiplying the input voltage by the specified gain (AV) and adding output

offset voltage. Gain is specified for IN_ and OSDFILL_ signal paths.

Note 2: Logic level characteristics apply to the following pins: DIN, DOUT, SCLK, CE, UPDATE, RESET, A3–A0, MODE, AOUT, and

OSDKEY_.

Note 3: Switching transient settling time is guaranteed by the settling time (tS) specification. Switching transient is a result of updat-

ing the switch matrix.

Note 4: Input test signal: 3.58MHz sine wave of amplitude 40IRE superimposed on a linear ramp (0 to 100IRE). IRE is a unit of

video-signal amplitude developed by the International Radio Engineers: 140IRE = 1.0V.

Note 5: All devices are 100% production tested at +25°C. Specifications over temperature limits are guaranteed by design.

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