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MAX4326 Просмотр технического описания (PDF) - Maxim Integrated

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MAX4326 Datasheet PDF : 17 Pages
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Single/Dual/Quad, Low-Cost, UCSP/SOT23,
Low-Power, Rail-to-Rail I/O Op Amps
__________ Applications Information
Rail-to-Rail Input Stage
Devices in the MAX4322/MAX4323/MAX4326/MAX4327/
MAX4329 family of high-speed amplifiers have rail-to-
rail input and output stages designed for low-voltage,
single-supply operation. The input stage consists of
separate NPN and PNP differential stages, which com-
bine to provide an input common-mode range extend-
ing to the supply rails. The PNP stage is active for input
voltages close to the negative rail, and the NPN stage
is active for input voltages near the positive rail. The
input offset voltage is typically below 250µV. The
switchover transition region, which occurs near VCC/2,
has been extended to minimize the slight degradation in
CMRR caused by the mismatch of the input pairs. Their
low offset voltage, high bandwidth, and rail-to-rail
common-mode range make these op amps excellent
choices for precision, low-voltage, data-acquisition
systems.
Since the input stage switches between the NPN and
PNP pairs, the input bias current changes polarity as
the input voltage passes through the transition region.
To reduce the offset error caused by input bias cur-
rents flowing through external source impedances,
match the effective impedance seen by each input
(Figures 1a, 1b). High-source impedances, together
with the input capacitance, can create a parasitic pole
that produces an underdamped signal response.
Reducing the input impedance or placing a small (2pF
to 10pF) capacitor across the feedback resistor
improves the response.
The MAX4322/MAX4323/MAX4326/MAX4327/MAX4329s
inputs are protected from large differential input voltages
by 1kseries resistors and back-to-back triple diodes
across the inputs (Figure 2). For differential input volt-
ages less than 1.8V, the input resistance is typically
500k. For differential input voltages greater than 1.8V,
the input resistance is approximately 2k, and the input
bias current is determined by the following equation:
R3
MAX4322/MAX4323
MAX4326/MAX4327
MAX4329
R1
R2
R3 = R1 R2
Figure 1a. Reducing Offset Error Due to Bias Current
(Noninverting)
1k
R3
MAX4322/MAX4323
MAX4326/MAX4327
MAX4329
R1
R2
R3 = R1 R2
Figure 1b. Reducing Offset Error Due to Bias Current
(Inverting)
1k
Figure 2. Input Protection Circuit
_______________________________________________________________________________________ 9

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