MAX3873 Просмотр технического описания (PDF) - Maxim Integrated
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MAX3873 Datasheet PDF : 12 Pages
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Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
The loop filter output controls the on-chip LC VCO run-
ning at either 2.488GHz or 2.67GHz. The VCO provides
low phase noise and is trimmed to the correct
frequency. Clock jitter generation is typically 2psRMS
within a jitter band of 12kHz to 20MHz.
Loss-of-Lock Monitor
A loss-of-lock (LOL) monitor is incorporated in the
MAX3873 to indicate either a loss of frequency lock or
the absence of incoming data. Under loss of lock con-
ditions, LOL may momentarily assert high due to noise.
Design Procedure
Setting the Loop Filter
The MAX3873 is designed for both regenerator and
receiver applications. Its fully integrated PLL is a clas-
sic second-order feedback system, with a loop band-
width (JBW) below 2.0MHz. The external capacitor, CF,
can be adjusted to set the loop damping. Figures 6 and
7 show the open-loop and closed-loop transfer func-
tions. The PLL zero frequency, fZ, is a function of exter-
nal capacitor CF, and can be approximated according
to:
fz
=
1
2π (3000Ω) CF
with CF expressed in F.
For an overdamped system, the jitter peaking (JP) of a
second-order system can be approximated by:
JP
=
20log 1 +
fz
JBW
For example, using CF = 2000pF results in jitter peak-
ing of 0.2dB. Reducing CF below 500pF might result in
PLL instability. The recommended value is CF = 0.01µF
to guarantee a maximum jitter peaking of less than
0.1dB. CF must be a low TC, high-quality capacitor of
type X7R or better.
FASTRACK Mode
The MAX3873 has a PLL fast-track (FASTRACK) mode
to decrease locking time in switched data applications.
In applications where the input data is switched from
one source to another, there is a brief period where
there is no valid data input to the MAX3873. In the
absence of input data, the PLL phase will slowly drift
from the ideal position. By enabling FASTRACK during
reacquisition, the time required to regain phase align-
ment is reduced. This is accomplished by increasing
the loop bandwidth by approximately 50%.
The bandwidth of the MAX3873 is also linearly depen-
dent upon the transition density of the input data. By
using a preamble of 1200 bits of a 1–0 pattern during
switching, the loop bandwidth is increased by a factor
of approximately 2 (see Figure 3). Thus by using a 1–0
pattern preamble and enabling FASTRACK, the PLL
bandwidth is increased by a factor of approximately 3,
resulting in the fastest possible reacquisition of phase
lock.
FASTRACK increases the rate at which the MAX3873
acquires the proper phase, assuming that the VCO is
already running at the proper frequency. On startup
conditions, however, the VCO frequency is significantly
different from the input data, and the time required to
lock to the incoming data is increased to approximately
1.0ms.
HO(j2πf) (dB)
CF = 0.01µF
fZ = 5.3kHz
CF = 2000pF
fZ = 26kHz
H(j2πf) (dB)
0
-3
CF = 2000pF
CF = 0.01µF
f (kHz)
1
10
100
1000
Figure 6. Open-Loop Transfer Function
1
10 100 1000
f (kHz)
Figure 7. Closed-Loop Transfer Function
8 _______________________________________________________________________________________
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