MAX3624A Просмотр технического описания (PDF) - Maxim Integrated
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MAX3624A Datasheet PDF : 12 Pages
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Low-Jitter, Precision Clock Generator
with Four Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless other-
wise noted.) (Notes 1, 2, and 3)
PARAMETER
SYMBOL
CONDITIONS
REF_IN SPECIFICATIONS (Input DC- or AC-Coupled)
Reference Clock Frequency
PLL enabled
PLL bypassed
Input-Voltage High
VIH
Input-Voltage Low
VIL
Input High Current
IIH
VIN = VCC
Input Low Current
Reference Clock Duty Cycle
IIL
VIN = 0V
PLL enabled
Input Capacitance
QA_C SPECIFICATIONS
Output High Voltage
VOH QA_C sourcing 12mA
Output Low Voltage
VOL QA_C sinking 12mA
Output Rise/Fall Time
(Notes 3 and 6)
Output Duty-Cycle Distortion
PLL enabled
PLL bypassed (Note 5)
Output Impedance
CLOCK OUTPUT AC SPECIFICATIONS
VCO Frequency Range
Random Jitter (Note 7)
12kHz to 20MHz
RJRMS
1.875MHz to 20MHz
Spurs Induced by Power-Supply
Noise (Notes 8, 9, 10)
LVPECL output
LVCMOS output
Deterministic Jitter Induced by
Power-Supply Noise
(Note 11)
Nonharmonic and Subharmonic
Spurs
Output Skew
Clock Output SSB Phase Noise
at 125MHz (Note 12)
Between QB0 and QB1
Between QA and QB0 or QB1,
PECL outputs
f = 1kHz
f = 10kHz
f = 100kHz
f = 1MHz
f > 10MHz
MIN TYP MAX UNITS
40.5
MHz
320
2.0
V
0.8
V
240
μA
-240
μA
30
70
%
2.5
pF
2.6
V
0.4
V
250 500 1000
ps
42
50
58
%
40
50
60
14
620
648
MHz
0.36
0.14
1.0
psRMS
-59
dBc
-47
4.6
psP-P
-70
15
20
-124
-125
-130
-145
-153
dBc
ps
dBc/H z
Note 1:
Note 2:
Note 3:
Note 4:
A series resistor of up to 10.5Ω is allowed between VCC and VCCA for filtering supply noise when system power-supply tol-
erance is VCC = 3.3V ±5%. See Figure 2.
Guaranteed up to 320MHz for LVPECL output.
Guaranteed up to 160MHz for LVCMOS output.
All outputs enabled and unloaded. IN_SEL set high.
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