MAX3671 Просмотр технического описания (PDF) - Maxim Integrated

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MAX3671

Low-Jitter Frequency Synthesizer with Selectable Input Reference

Maxim Integrated 

Low-Jitter Frequency Synthesizer

with Selectable Input Reference

Pin Description (continued)

PIN

NAME

FUNCTION

37

OUTA3

Clock Output A3, Differential LVPECL

38

OUTA3

39

OUTA2

Clock Output A2, Differential LVPECL

40

OUTA2

43

DA

Four-Level Control Input for A-Group Output Divider. See Table 2.

44

OUTA1

Clock Output A1, Differential LVPECL

45

OUTA1

46

OUTA0

Clock Output A0, Differential LVPECL

47

OUTA0

PLL Bypass Control, LVCMOS/LVTTL Input. Connect low or open for normal operation. Has

internal 90k
pulldown to GND. Connect high to bypass the PLL, connecting the selected

50

PLL_BYPASS reference clock directly to the clock outputs. In this mode, the clock qualification function

is not valid. To reduce spurious jitter in bypass mode, the internal VCO should be disabled

by shorting the CREG pin to GND.

51

RSVD3

Reserved. Connect to VCC.

54

RSVD4

Reserved. Leave pin open.

55

LOCK

PLL Lock Indicator, LVCMOS/LVTTL Output. Low indicates PLL is locked.

REFCLK1 Failure Indicator, LVCMOS/LVTTL Output. Low indicates REFCLK1 fails the clock

56

IN1FAIL

qualification. Once a failed clock is detected, the indicator status is latched and updated

every 128 PFD cycles (~ 2μs).

—

EP

Exposed Pad. Connect to supply ground for proper electrical and thermal performance.

Detailed Description

The MAX3671 integrates two differential LVPECL refer-

ence inputs with a 2:1 mux, a PLL with configurable

dividers, nine differential LVPECL clock outputs, and a

selectable external feedback input for zero-delay buffer

applications (see the Functional Diagram).

The two reference clock inputs are continuously moni-

tored for clock failure by the internal PLL and associat-

ed logic. If the primary clock fails, the user can switch

over to the secondary clock using the 2:1 mux.

The PLL accepts reference input frequencies of 62.5,

125, 250, or 312.5MHz and generates output frequen-

cies of 62.5, 125, 156.25, 250, or 312.5MHz. The nine

clock outputs are organized into two groups (A and B).

Each group has a configurable frequency divider and

output-enable control.

Phase-Locked Loop (PLL)

The PLL contains a phase-frequency detector (PFD),

charge pump (CP) with a lowpass filter, and voltage-

controlled oscillator (VCO). The PFD compares the

divided reference frequency to the divided VCO output

at 62.5MHz, and generates a control signal to keep the

VCO phase and frequency locked to the selected refer-

ence clock. Using a high-frequency VCO (2.5GHz) and

low-loop bandwidth (40kHz), the MAX3671 attenuates

reference clock jitter while maintaining lock and gener-

ates low-jitter clock outputs at multiple frequencies.

Typical jitter generation is 0.3psRMS (integrated 12kHz

to 20MHz).

To minimize supply noise-induced jitter, the VCO sup-

ply (VCC_VCO) is isolated from the core logic and out-

put buffer supplies. Additionally, the MAX3671 uses an

internal low-dropout (LDO) regulator to attenuate noise

from the power supply. This allows the device to

achieve excellent power-supply noise rejection, signifi-

cantly reducing the impact on jitter generation.

Clock Failure Conditions

The MAX3671 clock failure detection is performed

using the combination of amplitude qualification and

PLL frequency and phase-error qualification. The failure

status is indicated for REFCLK0 and REFCLK1 at

_______________________________________________________________________________________ 9

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