MAX3625A Просмотр технического описания (PDF) - Maxim Integrated

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MAX3625A

Low-Jitter, Precision Clock Generator with Three Outputs

Maxim Integrated 

Low-Jitter, Precision Clock

Generator with Three Outputs

ABSOLUTE MAXIMUM RATINGS

Supply Voltage Range VCC, VCCA,

VCCO_A, VCCO_B ..............................................-0.3V to +4.0V

Voltage Range at REF_IN, IN_SEL,

FB_SEL, SELA[1:0], SELB[1:0],

QA_OE, QB_OE, MR, BYPASS ..............-0.3V to (VCC + 0.3V)

Voltage Range at X_IN Pin ...................................-0.3V to +1.2V

Voltage Range at X_OUT Pin ......................-0.3V to (VCC - 0.6V)

Current into QA, QA, QB0, QB0, QB1, QB1 .....................-56mA

Continuous Power Dissipation (TA = +70°C)

24-Pin TSSOP (derate 13.9mW/°C above +70°C) .....1111mW

Operating Junction Temperature Range ...........-55°C to +150°C

Storage Temperature Range .............................-65°C to +160°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(VCC = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise

noted.) (Notes 1, 2, 3)

PARAMETER

SYMBOL

CONDITIONS

Power-Supply Current (Note 4)

IN_SEL = high

ICC

IN_SEL = low

CONTROL INPUT CHARACTERISTICS

(SELA[1:0], SELB[1:0], FB_SEL, IN_SEL, QA_OE, QB_OE, MR, BYPASS Pins)

Input Capacitance

CIN

Input Pulldown Resistor

RPULLDOWN Pins MR, FB_SEL

Input Logic Bias Resistor

RBIAS Pins SELA[1:0], SELB[1:0]

Input Pullup Resistor

RPULLUP Pins QA_OE, QB_OE, IN_SEL, BYPASS

LVPECL OUTPUTS (QA, QA, QB0, QB0, QB1, QB1 Pins)

Output High Voltage

VOH

Output Low Voltage

VOL

Peak-to-Peak Output-Voltage

Swing (Single-Ended)

(Note 2)

Clock Output Rise/Fall Time

20% to 80% (Note 2)

Output Duty-Cycle Distortion

PLL enabled

PLL bypassed (Note 5)

LVCMOS/LVTTL INPUTS

(SELA[1:0], SELB[1:0], FB_SEL, IN_SEL, QA_OE, QB_OE, MR, BYPASS Pins)

Input-Voltage High

Input-Voltage Low

Input High Current

Input Low Current

VIH

VIL

IIH

VIN = VCC

IIL

VIN = 0V

MIN TYP MAX UNITS

72

98

mA

74

2

pF

75

k

50

k

75

k

VCC -

1.13

VCC -

1.85

0.6

200

48

45

VCC -

0.98

VCC -

1.7

0.72

350

50

50

VCC -

0.83

VCC -

1.55

0.9

600

52

55

V

V

VP-P

ps

%

2.0

V

0.8

V

80

μA

-80

μA

2 _______________________________________________________________________________________

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