MAX3624 Просмотр технического описания (PDF) - Maxim Integrated
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MAX3624 Datasheet PDF : 12 Pages
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Low-Jitter, Precision Clock Generator
with Four Outputs
Table 1. Output Frequency Determination Chart
XO OR CMOS
INPUT
FREQUENCY
(MHz)
FEEDBACK
DIVIDER, M
VCO
FREQUENCY
(MHz)
OUTPUT
DIVIDER,
NA AND NB
2
4
25
25
625
5
8
10
25.78125
25
644.53125
4
2
4
26.04166
24
625
5
8
10
2
3
26.5625
24
637.5
4
6
12
2
19.44
32
622.08
4
8
2
38.88
(CMOS input)
16
622.08
4
8
OUTPUT
FREQUENCY
(MHz)
312.5
156.25
125
78.125
62.5
161.132812
312.5
156.25
125
78.125
62.5
318.75
212.5
159.375
106.25
53.125
311.04
155.52
77.76
311.04
155.52
77.76
APPLICATIONS
Ethernet
10Gbps Ethernet
Ethernet
Fibre Channel
SONET/SDH
SONET/SDH
Output Divider Configuration
Table 2 shows the input settings required to set the out-
put dividers. Leakage in the OPEN case must be less
than 1µA. Note that when the MAX3624 is in bypass
mode (BYPASS set low), the output dividers are auto-
matically set to divide by 1.
Table 2. Output Divider Configuration Chart
INPUT
SELA1/SELB1
SELA0/SELB0
0
0
0
1
1
0
1
1
1
OPEN
OPEN
1
0
OPEN
OPEN
0
OPEN
OPEN
NA/NB DIVIDER
/ 2*
/ 3*
/4
/5
/6
/8
/ 10
/ 12
/ 1*
*Maximum guaranteed output frequency is 160MHz for CMOS
and 320MHz for LVPECL output.
8 _______________________________________________________________________________________
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