MAX3624UTJ Просмотр технического описания (PDF) - Maxim Integrated

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MAX3624UTJ

Low-Jitter, Precision Clock Generator with Four Outputs

Maxim Integrated 

Low-Jitter, Precision Clock Generator

with Four Outputs

DISABLE

VDDO_A

10Ω

IN

QAC

10Ω

ESD

STRUCTURES

Figure 9. Simplified LVCMOS Output Circuit Schematic

Layout Considerations

The inputs and outputs are critical paths for the

MAX3624, and care should be taken to minimize dis-

continuities on these transmission line. Here are some

suggestions for maximizing the MAX3624’s perfor-

mance:

• An uninterrupted ground plane should be posi-

tioned beneath the clock I/Os.

• Ground pin vias should be placed close to the IC

and the input/output interfaces to allow a return

current path to the MAX3624 and the receive

devices.

• Supply decoupling capacitors should be placed

close to the MAX3624 supply pins.

• Maintain 100Ω differential (or 50Ω single-ended)

transmission line impedance out of the MAX3624.

• Use good high-frequency layout techniques and

multilayer boards with an uninterrupted ground

plane to minimize EMI and crosstalk.

Refer to the MAX3624 Evaluation Kit for more information.

Exposed-Pad Package

The exposed pad on the 32-pin TQFN package pro-

vides a very low inductance path for return current trav-

eling to the PCB ground plane. The pad is also

electrical ground on the MAX3624 and must be sol-

dered to the circuit board ground for proper electrical

performance.

Pin Configuration

TOP VIEW

32 31 30 29 28 27 26 25

VCCO_B 1

GND 2

+

24 GND

23 QB1_OE

QB0_OE 3

22 SELA1

SELB1 4

SELB0 5

MAX3624

21 SELA0

20 QA_OE

QAC_OE 6

MR 7

*EP

19 GND

18 VCC

GNDO_A 8

17 VCCA

9 10 11 12 13 14 15 16

THIN QFN-EP

(5mm × 5mm)

*EXPOSED PAD CONNECTED TO GROUND.

Chip Information

TRANSISTOR COUNT: 10,780

PROCESS: BiCMOS

______________________________________________________________________________________ 11

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