MAX3420E Просмотр технического описания (PDF) - Maxim Integrated
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MAX3420E Datasheet PDF : 23 Pages
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MAX3420E
USB Peripheral Controller with SPI Interface
Pin Configurations
TOP VIEW
TOP VIEW
18 17 16 15 14 13
XI 19
XO 20
GPIN0 21
GPIN1 22
MAX3420E
GPIN2 23
GPIN3 24
*EP
+
123456
12 GPX
11 MOSI
10 MISO
9 SS
8 SCLK
7 RES
TQFN
*CONNECT EXPOSED PAD TO GND.
24 23 22 21 20 19 18 17
N.C. 25
XI 26
XO 27
N.C. 28
GPIN0 29
MAX3420E
GPIN1 30
GPIN2 31
GPIN3 32
+
12345678
16 N.C.
15 GPX
14 MOSI
13 MISO
12 SS
11 SCLK
10 RES
9 N.C.
LQFP
Pin Description
PIN
TQFN-EP LQFP
1
1
2
2
3
3, 4
4, 14
5
6
5, 6, 18, 19
7
8
7
10
8
11
9
12
NAME
GPOUT0
GPOUT1
VL
GND
GPOUT2
GPOUT3
RES
SCLK
SS
INPUT/
OUTPUT
FUNCTION
Output
General-Purpose Push-Pull Outputs. GPOUT3–GPOUT0 logic levels are
referenced to the voltage on VL. The SPI master controls the GPOUT3–GPOUT0
states by writing to bit 3 through bit 0 of the IOPINS (R20) register.
Input
Input
Level-Translator Reference Voltage. Connect VL to the system’s 1.71V to 3.6V
logic-level power supply. Bypass VL to ground with a 0.1µF capacitor as close to
the VL pin as possible.
Ground
Output
General-Purpose Push-Pull Outputs. GPOUT3–GPOUT0 logic levels are
referenced to the voltage on VL. The SPI master controls the GPOUT3–GPOUT0
states by writing to bit 3 through bit 0 of the IOPINS (R20) register.
Input
Device Reset. Drive RES low to clear all of the internal registers except for
PINCTL (R17), USBCTL (R15), and SPI logic. See the Device Reset section for a
description of resets available on the MAX3420E. Note: The MAX3420E is
internally reset if either VCC of VL is not present. The register file is not
accessible under these conditions.
Input
SPI Serial-Clock Input. An external SPI master supplies this clock with
frequencies up to 26MHz. The logic level is referenced to the voltage on VL.
Data is clocked into the SPI slave interface on the positive edge of SCLK. Data
Is clocked out of the SPI slave interface on the falling edge of SCLK.
Input
SPI Slave-Select Input. The SS logic level is referenced to the voltage on VL.
When SS is driven high, the SPI slave interface is not selected and SCLK
transitions are ignored. An SPI transfer begins with a high-to-low SS transition
and ends with a low-to-high SS transition.
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