MAX3280 Просмотр технического описания (PDF) - Maxim Integrated

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MAX3280

±15kV ESD-Protected 52Mbps, 3V to 5.5V, SOT23 RS-485/RS-422 True Fail-Safe Receivers

Maxim Integrated 

±15kV ESD-Protected 52Mbps, 3V to 5.5V, SOT23

RS-485/RS-422 True Fail-Safe Receivers

provide the same clock to their respective circuits.

Thus, minimal package-to-package skew is critical. The

skew must be kept well below the period of the clock

signal to ensure that all of the circuits on the network

are synchronized.

128 Receivers on the Bus

The standard RS-485 input impedance is 12kΩ (one-

unit load). The standard RS-485 transmitter can drive

32 unit loads. The MAX3280E/MAX3281E/MAX3283E/

MAX3284E present a 1/4-unit-load input impedance

VOH

RO

VOL

1V A

VCC/2

tPHL

OUTPUT

tPLH

-1V

B

fIN = 1MHz

tr, tf ≤ 3ns

INPUT

Figure 1. Receiver Propagation Delay

1.5V

-1.5V

VCC/2

S3

VID

R

(48kΩ), which allows up to 128 receivers on the bus.

Any combination of these RS-485 receivers with a total

of 32 unit loads can be connected to the same bus.

Thermal Protection

The MAX3280E/MAX3281E/MAX3283E/MAX3284E fea-

ture thermal protection. Thermal protection sets the out-

put stage in high-impedance mode when a short circuit

occurs at the output, limiting both the power dissipation

and temperature. The thermal temperature threshold is

+165°C, with a hysteresis of 20°C.

Test Circuits/Timing Diagrams

S1

1kΩ

VCC

S2

CL

GENERATOR

50Ω

EN

OUT

EN

OUT 0.25V

tPRZH

VCC/2

tPRHZ

VCC/2

VCC

S1 OPEN

S2 CLOSED

S3 = 1.5V

0

VOH

VCC/2

0

VCC

S1 OPEN

S2 CLOSED

S3 = 1.5V

0

VOH

EN

OUT

EN

OUT

0

FOR MAX3281E THE ENABLE SIGNAL IS INVERTED.

Figure 2. MAX3281E/MAX3283E Receiver Enable/Disable Timing

VCC/2

tPRZL

VCC/2

VCC/2

tPRLZ

0.25V

VCC

S1 CLOSED

S2 OPEN

S3 = -1.5V

0

VCC

VOL

VCC

S1 CLOSED

S2 OPEN

S3 = -1.5V

0

VCC

VOL

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