MAX17101ETJ Просмотр технического описания (PDF) - Maxim Integrated
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MAX17101ETJ Datasheet PDF : 31 Pages
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Dual Quick-PWM, Step-Down Controller
with Low-Power LDO, RTC Regulator
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, no load on LDO, RTC, OUT1, OUT2, and REF, VIN = 12V, VDD = VCC = VSECFB = 5V, VREFIN2 = 1.0V, BYP =
LDOSEL = GND, ONLDO = IN, ON1 = ON2 = VCC, TA = -40°C to +85°C, unless otherwise noted.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
OUT2 Undervoltage-Protection
Trip Threshold
VUVP(OUT2) With respect to error-comparator threshold
60
80
%
PGOOD2 Lower Trip Threshold
With respect to error-comparator threshold,
falling edge, hysteresis = 2%
-20
-10
%
PGOOD2 Output-Low Voltage
VOUT2 = VREFIN2 - 150mV (PGOOD2 low
impedance), ISINK = 4mA
CURRENT LIMIT
ILIM_ Adjustment Range
VILIM
0.2
Valley Current-Limit Threshold
(Adjustable)
VVALLEY VAGND - VLX_
RILIM_ = 100k
RILIM_ = 200k
40
85
GATE DRIVERS
DH_ Gate Driver On-Resistance
RDH
BST1 - LX1 and BST2 - LX2 forced to 5V
DL1, DL2; high state
DL_ Gate Driver On-Resistance
RDL
DL1, DL2; low state
0.4
V
2.0
V
60
mV
115
3.5
4.5
1.5
INPUTS AND OUTPUTS
TON Input Logic Levels
SKIP Input Logic Levels
ON_ Input Logic Levels
ONLDO Input Logic Levels
High
REF or open
Low
High (forced PWM)
Open (ultrasonic)
Low (skip)
High (SMPS on)
Low (SMPS off)
High (SMPS on)
Low (SMPS off)
VCC -
0.4V
1.6
VCC -
0.4V
1.6
2.4
2.4
V
3.0
0.4
3.0
V
0.4
V
0.8
V
0.8
Note 1: DC output accuracy specifications refer to the threshold of the error comparator. When the inductor is in continuous conduc-
tion, the MAX17101 regulates the valley of the output ripple, so the actual DC output voltage is higher than the trip level by
50% of the output ripple voltage. In discontinuous conduction (IOUT < ILOAD(SKIP)), the output voltage has a DC regulation
level higher than the error-comparator threshold by approximately 1.5% due to slope compensation.
Note 2: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = PGND, VBST = 5V,
and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times might be differ-
ent due to MOSFET switching speeds.
Note 3: Specifications to TA = -40°C are guaranteed by design and not production tested.
Note 4: Specifications increased by 1Ω to account for test measurement error.
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