MAS9078BTC2(2003) Просмотр технического описания (PDF) - Micro Analog systems

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Компоненты Описание

производитель

MAS9078BTC2
(Rev.:2003)

AM Receiver IC

Micro Analog systems 

TYPICAL APPLICATION

Note 1

Ferrite-

Antenna RFI

X1

QO

QI

AGC Amplifier

DA9078.002

17 April 2003

AON (=AGC on)

Demodulator

&

Comparator

OUT

Receiver

output

1.4 V

VDD

Power Supply/Biasing

VSS

PDN

AGC DEC

Note 3

Power Down /

Fast Startup

Control

Note 2

CAGC

10 uF

CDEM

47 nF

Note 1: Crystal

The crystal as well as ferrite antenna frequencies are chosen according to the time-signal system (Table 1). The

crystal shunt capacitance C0 should be matched as well as possible with the internal shunt capacitance

compensation capacitance CC. MAS9078 has five compensation capacitance options. Capacitance values and

suitable crystals are described in Table 2. See also Ordering Information (p.10).

Time-Signal System Location

Antenna Frequency

DCF77

MSF

WWVB

JJY

Table 1

Germany

77.5 kHz

United Kingdom

60 kHz

USA

60 kHz

Japan

40 kHz and 60 kHz

Time-Signal System Frequencies

Recommended Crystal Frequency

77.503 kHz

60.003 kHz

60.003 kHz

40.003 kHz and 60.003 kHz

Device

MAS9078B1

MAS9078B2

MAS9078B3

MAS9078B4

MAS9078B5

Table 2

CC

Crystal Description

0.75 pF

1.25 pF

1.625 pF

For single low C0 crystal (Nominal value)

For single high C0 crystal

For two parallel low C0 crystals (dual band receiver)

2.5 pF

For two parallel high C0 crystals (dual band receiver)

3.875 pF Any crystal with parallel external compensation capacitor

Compensation Capacitance Options

Note 2: AGC Capacitor

The AGC and DEC capacitors must have low leakage currents due to very small 40 nA signal currents through

the capacitors. The insulation resistance of these capacitors should be higher than 70 MΩ. Also probes with at

least 100 MΩ==impedance should be used for voltage probing of AGC and DEC pins.

Note 3: Power Down / Fast Startup Control

Both power down and fast startup are controlled using the PDN pin. The device is in power down (turned off) if

PDN = VDD and in power up (turned on) if PDN = VSS. Fast startup is triggered by the falling edge of PDN

signal, i.e., controlling device from power down to power up. The startup time without using the fast startup

control can be several minutes but with fast startup it is shortened typically to 12 s.

4 (10)

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