MAS6180 Просмотр технического описания (PDF) - Micro Analog systems
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MAS6180 Datasheet PDF : 9 Pages
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MAS6180 PAD LAYOUT
DA6180.001
27 December, 2006
VDD
QOP
QOM
QI
AGC
OUT
1070 µm
VSS pad
bonded
first!
VSS
RFIM
RFIP
PDN
AON
DEC
MAS6180Ax,
x = 1, 2, 5
DIE size = 1.07 mm x 1.37 mm; PAD size = 80 µm x 80 µm
Note: Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left
floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly
are recommended to be performed in ESD protected area.
Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.
Pad Identification
Power Supply Voltage
Positive Quartz Filter Output for Crystal
Negative Quartz Filter Output for Crystal
Quartz Filter Input for Crystal and External
Compensation Capacitor
AGC Capacitor
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down
Positive Receiver Input
Negative Receiver Input
Power Supply Ground
Name
VDD
QOP
QOM
QI
AGC
OUT
DEC
AON
PDN
RFIP
RFIM
VSS
X-coordinate
152 µm
152 µm
152 µm
152 µm
152 µm
152 µm
915 µm
915 µm
915 µm
915 µm
915 µm
915 µm
Y-coordinate
1137 µm
1002 µm
815 µm
629 µm
443 µm
257 µm
265 µm
451 µm
636 µm
824 µm
1010 µm
1158 µm
Note
1
2
3
4
5
5
Notes:
1) External crystal compensation capacitor pin QOM is connected only in MAS6180A5 version. It is left
unconnected in MAS6180A1 and A2 versions which have internal compensation capacitor.
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)
- the output is a current source/sink with |IOUT| > 5 µA
- at power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1 µA which is switched off at power down
4) PDN = VSS means receiver on; PDN = VDD means receiver off
Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
5) Receiver inputs RFIP and RFIM have both 600 kΩ biasing resistors towards VDD
2 (9)
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