HT16512 Просмотр технического описания (PDF) - Holtek Semiconductor
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HT16512 Datasheet PDF : 11 Pages
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HT16512
A.C. Characteristics
Symbol
Parameter
tPHL
Propagation Delay Time
tPLH
tr1
Rise Time
tr2
tf
Fall Time
tmax
Maximum Clock Frequency
Ci
Input Capacitance
tCW
Clock Pulse Width
tSW
Strobe Pulse Width
tSU
Data Setup Time
th
Data Hold Time
tCS
Clock-Strobe Time
tW
Wait Time
Test Conditions
VDD
Conditions
Min.
5V CLK®DO
¾
5V CL=15pF, RL=10kW
¾
5V CL=300pF, S0~S10
¾
5V
CL=300pF, G0~G5,
S11/G10~S15/G6
¾
5V CL=300pF, Sn, Gn
¾
5V Duty=50%
1
5V
¾
¾
5V
¾
400
5V
¾
1
5V
¾
100
5V
¾
100
5V CLK rising edge to CS rising edge 1
5V CLK rising edge to CLK falling edge 1
Ta=25°C
Typ. Max. Unit
¾ 100 ns
¾ 300 ns
¾
2
ms
¾ 0.5 ms
¾ 120 ms
¾ ¾ MHz
¾ 15 pF
¾ ¾ ns
¾ ¾ us
¾ ¾ ns
¾ ¾ ns
¾ ¾ ms
¾ ¾ ms
Functional Description
Display RAM and Display Mode
The static display RAM is organized into 22´8 bits and
stores the data transmitted from an external device to
the HT16512 through a serial interface. The contents of
the RAM are directly mapped to the contents of the VFD
driver. Data in the RAM can be accessed through the
data setting, address setting and display control com-
mands. It is assigned addresses in 8-bit unit as follows:
S0 ~ S3 S4
A d d re s s : 0 0 H
02H
04H
06H
08H
0A H
0C H
0E H
10H
12H
14H
~ S 7 S 8 ~ S 11 S 12 ~ S 15
01H
D ig it0
03H
D ig it1
05H
D ig it2
07H
D ig it3
09H
D ig it4
0B H
D ig it5
0D H
D ig it6
0FH
D ig it7
11H
D ig it8
13H
D ig it9
15H
D ig it1 0
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
Dimming Control
HT16512 provides 8-step dimmer function on display by
controlling the 3-bit binary command code. The full
pulse width of grid signal is divides into 16 uniform sec-
tions by PWM (pulse width modulation) technology.
The 16 uniform sections available form 8 steps dimmer
via 3-bit binary code. The 8-step dimmer includes 1/16,
2/16, 4/16, 10/16, 11/16, 12/16, 13/16 and 14/16. The
1/16 pulse width indicates minimum lightness. The
14/16 pulse width represents maximum lightness. (Re-
fer to the display control command).
Key Matrix and Key-Input Data Storage RAM
The key matrix scans the series key states at each level
of the key strobe signal (S0/K0~S5/K5) output of the
HT16512. The key strobe signal outputs are
time-multiplexed signals from S0/K0~S5/K5. The states
of inputs K0~K3 are sampled by strobe signal
S0/K0~S5/K5 and latched into the register.
The key matrix is made up of a 6´4 matrix, as shown be-
low.
S 0 /K 0 S 1 /K 1 S 2 /K 2 S 3 /K 3 S 4 /K 4 S 5 /K 5
K0
K1
K2
K3
D e ta il
K e y m a tr ix
Rev. 1.50
4
May 7, 2010
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