AS7C164-15(2002) Просмотр технического описания (PDF) - Alliance Semiconductor
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AS7C164-15 Datasheet PDF : 8 Pages
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Parameter
Symbol
Test conditions
Min
Max
Unit
VCC for data retention
Data retention current
Chip enable to data retention time
Operation recovery time
VDR
ICCDR
tCDR
tR
2.0
–
V
VCC = 2.0V
–
60
µA
CE1 ≥ VCC–0.2V or
CE2 ≤ 0.2V
0
–
ns
tRC
–
ns
'DWD UHWHQWLRQ ZDYHIRUP
VCC
CE1
CS2
VCC
tCDR
VIH
VIH
tCDR
Data retention mode
VDR ≥ 2.0V
VDR
VDR
VCC
tR
VIH
VIH
tR
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- Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
+5V
+3.0V
90%
90%
10%
GND
2ns
10%
Figure A: Input pulse
DRXW
255Ω
480Ω
C(14)
GND
Figure B: 5V Output loDG
Thevenin Equivalent:
168Ω
DRXW
+1.728V (5V)
+5V
DRXW
255Ω
320Ω
C(14)
GND
Figure C: 3.3V Output load
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1 During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, and C.
4 tCLZ and tCHZ are specified with CL = 5pF as in Figures B or C. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6 WE is High for read cycle.
7 CE1 and OE are Low and CE2 is High for read cycle.
8 Address valid prior to or coincident with CE1 transition Low and CE2 transition High.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE1 or WE must be High or CE2 Low during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 2V data retention applies to the commercial operating range only.
14 C = 30pF, except on High Z and Low Z parameters, where C = 5pF.
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