M80C186XL16 Просмотр технического описания (PDF) - Intel

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M80C186XL16

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR

Intel 

M80C186XL

Symbol

LCS

(Continued)

MCS0 PEREQ

MCS1 ERROR

MCS2

MCS3 NPS

PCS0

PCS1

PCS2

PCS3

PCS4

PCS5 A1

PCS6 A2

DT R

DEN

NC

Table 1 M80C186XL Pin Description (Continued)

PGA

Pin No

Type

Name and Function

UCS and LCS are sampled upon the rising edge of RES If both

pins are held low the M80C186XL will enter ONCE Mode In ONCE

Mode all pins assume a high impedance state and remain so until a

subsequent RESET LCS has a weak internal pullup that is active

only during RESET to ensure that the M80C186XL does not enter

ONCE mode inadvertently

38

O I Mid-Range Memory Chip Select signals are active LOW when a

37

O I memory reference is made to the defined mid-range portion of

36

O memory (8K – 512K) These lines do not float during bus HOLD The

35

O

address ranges activating MCS0 – 3 are software programmable

In Enhanced Mode MCS0 becomes a PEREQ input (Processor

Extension Request) When connected to the Math Coprocessor

this input is used to signal the M80C186XL when to make numeric

data transfers to and from the coprocessor MCS3 becomes NPS

(Numeric Processor Select) which may only be activated by

communication to the 80C187 MCS1 becomes ERROR in

Enhanced Mode and is used to signal numerics coprocessor errors

MCS0 PEREQ and MCS1 ERROR have weak internal pullups

which are active during reset

25

O Peripheral Chip Select signals 0 – 4 are active LOW when a

27

O reference is made to the defined peripheral area (64K byte I O or 1

28

O MByte memory space) These lines do not float during bus HOLD

29

O

The address ranges activating PCS0 – 4 are software

30

O

programmable

31

O Peripheral Chip Select 5 or Latched A1 may be programmed to

provide a sixth peripheral chip select or to provide an internally

latched A1 signal The address range activating PCS5 is software-

programmable PCS5 A1 does not float during bus HOLD When

programmed to provide latched A1 this pin will retain the previously

latched value during HOLD

32

O Peripheral Chip Select 6 or Latched A2 may be programmed to

provide a seventh peripheral chip select or to provide an internally

latched A2 signal The address range activating PCS6 is software-

programmable PCS6 A2 does not float during bus HOLD When

programmed to provide latched A2 this pin will retain the previously

latched value during HOLD

40

O Data Transmit Receive controls the direction of data flow through

an external data bus transceiver When LOW data is transferred to

the M80C186XL When HIGH the M80C186XL places write data on

the data bus DT R floats during a bus hold or reset

39

O Data Enable is provided as a data bus transceiver output enable

DEN is active LOW during each memory and I O access (including

80C187 access) DEN is HIGH whenever DT R changes state

During RESET DEN is driven HIGH for one clock then floated

DEN also floats during HOLD

Not connected To maintain compatibility with future products do

not connect to these pins

9

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