M80C186XL Просмотр технического описания (PDF) - Intel

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производитель

M80C186XL

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR

Intel 

M80C186XL

Symbol

VCC

VSS

RESET

PGA

Pin No

9

43

26

60

57

X1

59

X2

58

CLKOUT

56

RES

24

TEST BUSY

47

Table 1 M80C186XL Pin Description

Type

Name and Function

I

System Power a5 volt power supply

I

I

System Ground

I

O RESET Output indicates that the M80C186XL CPU is being reset and

can be used as a system reset It is active HIGH synchronized with

the processor clock and lasts an integer number of clock periods

corresponding to the length of the RES signal Reset goes inactive 2

clockout periods after RES goes inactive When tied to the TEST

BUSY pin RESET forces the M80C186XL into enhanced mode

RESET is not floated during bus hold

I

Crystal Inputs X1 and X2 provide external connections for a

O fundamental mode or third overtone parallel resonant crystal for the

internal oscillator X1 can connect to an external clock instead of a

crystal In this case minimize the capacitance on X2 The input or

oscillator frequency is internally divided by two to generate the clock

signal (CLKOUT)

O Clock Output provides the system with a 50% duty cycle waveform

All device pin timings are specified relative to CLKOUT CLKOUT is

active during reset and bus hold

I

An active RES causes the M80C186XL to immediately terminate its

present activity clear the internal logic and enter a dormant state

This signal may be asynchronous to the M80C186XL clock The

M80C186XL begins fetching instructions approximately 6 clock

cycles after RES is returned HIGH For proper initialization VCC must

be within specifications and the clock signal must be stable for more

than 4 clocks with RES held LOW RES is internally synchronized

This input is provided with a Schmitt-trigger to facilitate power-on RES

generation via an RC network

I O The TEST pin is sampled during and after reset to determine whether

the M80C186XL is to enter Compatible or Enhanced Mode Enhanced

Mode requires TEST to be HIGH on the rising edge of RES and LOW

four CLKOUT cycles later Any other combination will place the

M80C186XL in Compatible Mode During power-up active RES is

required to configure TEST BUSY as an input A weak internal pullup

ensures a HIGH state when the input is not externally driven

TEST In Compatible Mode this pin is configured to operate as TEST

This pin is examined by the WAIT instruction If the TEST input is

HIGH when WAIT execution begins instruction execution will

suspend TEST will be resampled every five clocks until it goes LOW

at which time execution will resume If interrupts are enabled while the

M80C186XL is waiting for TEST interrupts will be serviced

BUSY In Enhanced Mode this pin is configured to operate as

BUSY The BUSY input is used to notify the M80C186XL of Math

Coprocessor activity Floating point instructions executing in the

M80C186XL sample the BUSY pin to determine when the Math

Coprocessor is ready to accept a new command BUSY is active

HIGH

5

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