MC80C86 Просмотр технического описания (PDF) - Intel

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MC80C86

16-BIT CHMOS MICROPROCESSOR

Intel 

M80C86 M80C86-2

INTERNAL ARCHITECTURE

The internal functions of the M80C86 processor are

partitioned logically into two processing units The

first is the Bus Interface Unit (BIU) and the second is

the Execution Unit (EU) as shown in the block dia-

gram of Figure 1

These units can interact directly but for the most

part perform as separate asynchronous operational

processors The bus interface unit provides the func-

tions related to instruction fetching and queuing op-

erand fetch and store and address relocation This

unit also provides the basic bus control The overlap

of instruction pre-fetching provided by this unit

serves to increase processor performance through

improved bus bandwidth utilization Up to 6 bytes of

the instruction stream can be queued while waiting

for decoding and execution

The instruction stream queuing mechanism allows

the BIU to keep the memory utilized very efficiently

Whenever there is space for at least 2 bytes in the

queue the BIU will attempt a word fetch memory

cycle This greatly reduces ‘‘dead time’’ on the

memory bus The queue acts as a First-In-First Out

(FIFO) buffer from which the EU extracts instruction

bytes as required If the queue is empty (following a

branch instruction for example) the first byte into

the queue immediately becomes available to the EU

The execution units receives pre-fetched instruc-

tions from the BIU queue and provides un-relocated

operand addresses to the BIU Memory operands

are passed through the BIU for processing by the

EU which passes results to the BIU for storage See

the Instruction Set description for further register set

and architectural descriptions

NOTE

Additional information on memory organization re-

quirements for supporting minimum and maximum

modes bus operation basic system timing and ex-

ternal interface of the M80C86 is described in the

Microsystems Components Handbook

DEVIATION DESCRIPTION

A 20 – 25 ns glitch occurs on the 80C86 80C88 RD

pin immediately following a read cycle The problem

has been fully characterized with the following re-

sults

1 The read cycle must be 4 clocks followed by 2

passive clocks

2 Cycle following the read cycle must be a data

read write or an I O read write

3 The of bytes in the queue required to cause

the glitch varies by instruction

4 The glitch appears on the falling edge of the first

passive clock

5 The magnitude of the glitch depends on the ca-

pacitive loading of the RD pin

6 The glitch occurs for both Min and Max mode

operations

7 VCC variations from 4 5V through 5 5V have no

effect on the glitch

8 Temperature variations (within allowed tempera-

ture range) also have no effect on the glitch

IMPACT ON SYSTEM DESIGN

Systems which use the RD strobe to clock a state

machine or any other edge triggered device are

most vulnerable and most likely to malfunction

The problem may also impact other Min mode sys-

tems particularly those in which the system address

latches are enabled all the time (such as the exam-

ple minimum mode system illustrated in the 80C86

data sheet) In such designs the RD signal is used

to turn off the output buffers of the memory and pe-

ripheral devices connected to the local bus at the

end of a bus cycle A false pulse on the RD pin in a

TP or a T1 state following a read cycle may not allow

for sufficient recovery time for a previously accessed

device The probability of a failure is higher for low

speed designs using slow memory and peripheral

devices which require high recovery times between

successive accesses The problem will not be seen

if the address latches are disabled at the end of any

bus cycle since all the devices connected to the bus

will then be deselected when the false pulse occurs

Most Max mode systems do not use the RD signal

and are therefore not likely to be affected

7

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