M7020R-083ZA1 Просмотр технического описания (PDF) - STMicroelectronics

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Компоненты Описание

производитель

M7020R-083ZA1

32K x 68-bit Entry NETWORK SEARCH ENGINE

STMicroelectronics 

M7020R

SEARCH COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

68-bit Configuration with Single Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Hardware Diagram for a Table with One Device (Figure 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Timing Diagram for a 68-bit Configuration SEARCH for One Device (Figure 20.) . . . . . . . . . . . . . 38

x68 Table with One Device (Figure 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, 1 Device (Table 25.) . . . . . . 39

Shift of SSF and SSV from SADR (Table 26.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

68-bit SEARCH on Tables Configured as x68 Using up to Eight M7020R Devices . . . . . . . . . 40

Hit/Miss Assumption (Table 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Hardware Diagram for a Table with Eight Devices (Figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

x68 Table with Eight Devices (Figure 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Timing Diagrams for x68 Using up to Eight M7020R Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

68-bit SEARCH For Device 0 (Figure 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

68-bit SEARCH For Device 1 (Figure 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

68-bit SEARCH For Device 7 (Last Device) (Figure 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, Up to 8 Devices (Table 28.) 46

Shift of SSF and SSV from SADR (Table 29.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

68-bit SEARCH on Tables Configured as x68 Using Up To 31 M7020R Devices. . . . . . . . . . . 46

Hit/Miss Assumption (Table 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Hardware Diagram for a Table with 31 Devices (Figure 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Hardware Diagram for a Block of Up To Eight Devices (Figure 28.) . . . . . . . . . . . . . . . . . . . . . . . . 49

x68 Table with 31 Devices (Figure 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Timing Diagrams for x68 Using Up To 31 M7020R Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Each Device in Block Number 0 (Miss on Each Device) (Figure 30.) . . . . . . . . . . . . . . . . . . . . 51

Each Device Above the Winning Device in Block Number 1 (Figure 31.) . . . . . . . . . . . . . . . . . 52

Globally Winning Device in Block Number 1 (Figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Devices Below the Winning Device in Block Number 1 (Figure 33.). . . . . . . . . . . . . . . . . . . . . 54

Devices Above the Winning Device in Block Number 2 (Figure 34.) . . . . . . . . . . . . . . . . . . . . 55

Globally Winning Device in Block Number 2 (Figure 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Devices Below the Winning Device in Block Number 2 (Figure 36.). . . . . . . . . . . . . . . . . . . . . 57

Devices Above the Winning Device in Block Number 3 (Figure 37.) . . . . . . . . . . . . . . . . . . . . 58

Globally Winning Device in Block Number 3 (Figure 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Devices Below the Winning Device in Block Number 3 (not Device 30 - Last Device) . . . . . . . 60

Device 6 in Block Number 3 (Device 30 in Depth-Cascaded Table) (Figure 40.) . . . . . . . . . . . 61

Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, Up to 31 Devices . . . . . . . . 62

Shift of SSF and SSV from SADR (Table 32.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

136-bit Configuration with Single Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Hardware Diagram for a Table with 1 Device (Figure 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Timing Diagram for a 136-bit SEARCH for One Device (Figure 42.). . . . . . . . . . . . . . . . . . . . . . . . 64

x136 Table with One Device (Figure 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Latency of SEARCH from Instruction to SRAM Access Cycle, 136-bit, 1 Device (Table 33.) . . . . . 65

Shift of SSF and SSV from SADR (Table 34.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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