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M64894FP Просмотр технического описания (PDF) - Renesas Electronics

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M64894FP Datasheet PDF : 13 Pages
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M64894FP/GP
Pin Arrangement
M64894FP/GP
fin 1
GND 2
VCC1 3
VCC2 4
BS4 5
BS3 6
BS2 7
BS1 8
16 Xin
15 ADS
14 SDA
13 SCL
12 ADC
11 VCC3
10 Vtu
9 Vin
(Top view)
Outline: PRSP0016DA-A (16P2S-A) [FP]
PRSP0016JA-A (16P2Z-A) [GP]
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
Symbol
fin
GND
VCC1
VCC2
BS4
BS3
BS2
BS1
Vin
Pin name
Prescaler input
GND
Power supply voltage 1
Power supply voltage 2
Band switching outputs
Filter input
(Charge pump output)
10 Vtu
Tuning output
11
VCC3
Power supply voltage 3
12 ADC/ftest AD converter input/
Test port
13 SCL
14 SDA
Clock input
Data input
15 ADS
16 Xin
Address switching input
This is connected to the
crystal oscillator
Function
Input for the VCO frequency.
Ground to 0 V.
Power supply voltage terminal. 5.0 V ± 0.5 V
Power supply for band switching, VCC1 to 13.2 V
PNP open collector method is used.
When the band switching data is “H”, the output is ON.
When it is “L”, the output is OFF.
This is the output terminal for the LPF input and charge pump
output. When the phase of the programmable divider output (f
1/N) is ahead compared to the reference frequency (fREF), the
“source” current state becomes active.
If it is behind, the “sink” current becomes active.
If the phases are the same, the high impedance state becomes
active.
This supplies the tuning voltage.
Power supply voltage for tuning voltage 28 to 35 V
A/D conversion of the input voltage.
In control byte data input, the programmable freq. Divider output
and reference freq. output is selected by the test mode.
Data is read into the shift register when the clock signal falls.
Input for band SW and programmable freq. divider set up.
In lead mode, it outputs lock detector output and power down flag
and a state of 5 level A/D converter.
Chip address sets it up with the input condition of terminal.
4.0 MHz crystal oscillator is connected.
Rev.2.00 Jun 14, 2006 page 3 of 12

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