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M5M5V216ATP Просмотр технического описания (PDF) - Renesas Electronics

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M5M5V216ATP Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
revision-03, 14.Jan.'03
M5M5V216ATP,RT
MITSUBISHI LSIs
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Vcc=2.7 ~ 3.6V, unless otherwise noted)
(1) TEST CONDITIONS
Supply v oltage
2.7V~3.6V
Input pulse
V IH= 2 . 4 V , V IL= 0 . 4 V
Input rise time and f all time 5ns
Ref erence lev el
Output loads
V OH=V OL= 1 . 5 V
Transition is measured ±500mV f rom
steady state voltage.(f or ten,t dis)
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
1TTL
DQ
CL
Including scope and
jig capacitance
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
t CR
ta(A)
ta(S)
ta(BC1)
ta(BC2)
ta(OE)
tdis(S)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S)
ten(BC1)
ten(BC2)
ten(OE)
tV(A)
Read cy cle time
Address access time
Chip select access time
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time af t er S high
Output disable time af t er BC1 high
Output disable time af t er BC2 high
Output disable time af t er OE high
Output enable time af ter S low
Output enable time af ter BC1 low
Output enable time af ter BC2 low
Output enable time af ter OE low
Data v alid time after address
5 5 HI
Limits
70HI
Min
Max
Min
Max
55
70
55
70
55
70
55
70
55
70
30
35
20
25
20
25
20
25
20
25
10
10
10
10
10
10
5
5
10
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Symbol
Parameter
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(BC1)
tsu(BC2)
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Write cy cle time
Write pulse width
Address setup time
Address setup time with respect to W
By te control 1 setup time
By te control 2 setup time
Chip select setup time
Data setup time
Data hold time
Write recov ery time
Output disable time f rom W low
Output disable time f rom OE high
Output enable time f rom W high
Output enable time f rom OE low
5 5 HI
Min
Max
55
45
0
50
50
50
50
25
0
0
20
20
5
5
Limits
Min
70
55
0
65
65
65
65
30
0
0
5
5
70HI
Max
25
25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4

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