M5M5V108DKV-70H Просмотр технического описания (PDF) - Renesas Electronics

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M5M5V108DKV-70H

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

Renesas Electronics 

7th.July.2000 Ver. 1.1

MITSUBISHI LSIs

M5M5V108DFP,VP,KV -70H

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

FUNCTION

The operation mode of the M5M5V108D series are determined by

a combination of the device control inputs S1,S2,W and OE.

Each mode is summarized in the function table.

A write cycle is executed whenever the low level W overlaps with

the low level S1 and the high level S2. The address must be set up

before the write cycle and must be stable during the entire cycle.

The data is latched into a cell on the trailing edge of W,S1 or

S2,whichever occurs first,requiring the set-up and hold time relative

to these edge to be maintained. The output enable input OE

directly controls the output stage. Setting the OE at a high level,

the output stage is in a high-impedance state, and the data bus

contention problem in the write cycle is eliminated.

A read cycle is executed by setting W at a high level and OE at a

low level while S1 and S2 are in an active state(S1=L,S2=H).

FUNCTION TABLE

S1 S2

XL

HX

LH

LH

LH

W OE Mode

DQ

ICC

X X Non selection High-impedance Stand-by

X X Non selection High-impedance Stand-by

LX

Write

Din

Active

HL

Read

Dout

Active

HH

High-impedance Active

Note 1: "H" and "L" in this table mean VIH and VIL, respectively.

2: "X" in this table should be "H" or "L".

When setting S1 at a high level or S2 at a low level, the chip are in

a non-selectable mode in which both reading and writing are

disabled. In this mode, the output stage is in a high- impedance

state, allowing OR-tie with other chips and memory expansion by

S1 and S2. The power supply current is reduced as low as the

stand-by current which is specified as ICC3 or ICC4, and the memory

data can be held at +2V power supply, enabling battery back-up

operation during power failure or power-down operation in the non-

selected mode.

BLOCK DIAGRAM

A3 9

A2 10

A5 7

A6 6

A7 5

A12 4

A14 3

A16 2

A15 31

*

17

18

15

14

13

12

11

10

7

131072 WORDS

X 8 BITS

( 512 ROWS

X128 COLUMNS

X 16BLOCKS )

*

21

22

23

25

26

27

28

29

13 DQ1

14 DQ2

15 DQ3

17 DQ4

18 DQ5

19 DQ6

DATA

INPUTS/

OUTPUTS

20 DQ7

21 DQ8

ADDRESS

INPUTS

A13 28 4

A8 27 3

A9 26 2

A11 25 1

A4 8 16

A1 11 19

A0 12 20

A10 23 31

CLOCK

GENERATOR

* Pin numbers inside dotted line show those of TSOP

WRITE

5

29 W CONTROL

INPUT

30

22 S1 CHIP

6

30 S2

SELECT

INPUTS

OUTPUT

32

24 OE ENABLE

INPUT

8

32 VCC

24

16

GND

(0V)

2

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