M5M5V416CWG-70HI Просмотр технического описания (PDF) - Renesas Electronics

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производитель

M5M5V416CWG-70HI

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

Renesas Electronics 

2002.04.18 Ver. 6.0

MITSUBISHI LSIs

M5M5V416CWG -55HI, -70HI

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

Write cycle (BC# control mode)

tCW

A 0~17

BC1#,BC2#

tsu (A)

tsu (BC1) or

tsu (BC2)

trec (W)

S1#

S2

W#

DQ1~16

(Note3)

(Note3)

(Note5)

(Note3)

(Note4)

tsu (D) th (D)

DATA IN

STABLE

(Note3)

(Note3)

(Note3)

Note 3: Hatching indicates the state is "don't care".

Note 4: A Write occurs during S1# low, S2 high ov erlaps BC1# and/or BC2# low and W# low.

Note 5: When the f alling edge of W# is simultaneously or prior to the f alling edge of BC1# and/or BC2# or the f alling edge of

S1# or rising edge of S2, the outputs are maintained in the high impedance state.

Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode.

6

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