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M5913B1

COMBINED SINGLE CHIP PCM CODEC AND FILTER

STMicroelectronics 

M5913

OUTPUT GAIN SET: DESIGN CONSIDERA-

TIONS (refer to figure 4)

PWRO+ and PWRO– are low impedance comple-

mentary outputs. The voltages at the nodes are:

VO at PWRO+

VO at PWRO

VO = VO+ VO– (total differential response)

R1 and R2 are a gain setting resistor network with

the center tap connected to the GSR input. A

value greater than 10KΩ and less than 100KΩ for

R1 + R2 is recommended because:

a) The parallel combination of R1 + R2 and RL

sets the total loading.

b) The total capacitance at the GSR input and the

parallel combination of R1 and R2 define a

time constant which has to be minimized to

avoid inaccuracies.

If VA represents the output voltage without any

gain setting network connected, you can have:

VO = AVA

where

A

=

1

4

+

+

(R1

(R1

/

/

R2)

R2)

For design purposes, a useful form is R1/R2 as a

function of A.

R1

/

R2

=

4A – 1

1–A

(allowable values for A are those which make

R1/R2 positive)

Examples are:

If A = 1 (maximum output), then

R1/R2 = ∞ or V(GSR) = VO;

i.e., GSR is tied to PWRO+

If A = 1/2. then

R1/R2 = 2

If A = 1/4 (minimum output) then

R1/R2 = 0 or V(GSR) = VO+;

i.e., GSR is tied to PWRO+

DC CHARACTERISTICS (Tamb

erwise specified) Typical values

=0

are

to 70oC,

for Tamb

=VC2C5o=C+a5nVd±no5m%i,nVaBl pBo=w–er5sVup±p5ly%v,aGluReDs.A

=

0V,unless

oth-

Symbol

Parameter

DIGITAL INTERFACE

IIL

Low Level Input Current

IIH

High Level Input Current

VIL

Input Low Voltage, Except CLKSEL

VIH Input High Voltage, Except CLKSEL

VOL Output Low Voltage

VOH Output High Voltage

VILO Input Low Voltage, CLKSEL (note 2)

VIIO Input Intermediate Voltage, CLKSEL

VIHO Input High Voltage, CLKSEL

COX Digital Output Capacitance (note 3)

CIN Digital Input Capacitance

Test Conditions

Min. Typ. Max. Unit

GRDD ≤ VIN ≤ VIL (note 1)

VIH ≤ VIN ≤ VCC

2.0

IOL = 3.2mA at DX, TSX and

SIGR

IOH = 9.6mA at DX

2.4

IOH = 1.2mA at SIGR

VBB

GRDD

-0.5

VCC -

0.5

5

5

10 µA

10 µA

0.8 V

V

0.4 V

V

VBB + V

0.5

0.5 V

VCC V

pF

10 pF

Notes:

1. VIN is the voltage on any digital pin.

2. SIGX and DCLKR are TTL level inputs between GRDD and VCC; they are also pinstraps for mode selection when tied to VBB.

Under these conditions VILO is the input low voltage requirement.

3. Timing parameters are guaranteed based on a 100pF load capacitance.

Up to eight digital outputs may be connected to a common PCM highway without buffering, assuming a board capacitance of 60pF.

7/17

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