M58WR128EB10ZB6T Просмотр технического описания (PDF) - STMicroelectronics

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M58WR128EB10ZB6T

128 Mbit (8Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory

STMicroelectronics 

M58WR128ET, M58WR128EB

SUMMARY DESCRIPTION

The M58WR128E is a 128 Mbit (8Mbit x16) non-

volatile Flash memory that may be erased electri-

cally at block level and programmed in-system on

a Word-by-Word basis using a 1.65V to 2.2V VDD

supply for the circuitry and a 1.65V to 3.3V VDDQ

supply for the Input/Output pins. An optional 12V

VPP power supply is provided to speed up custom-

er programming.

The device features an asymmetrical block archi-

tecture. M58WR128E has an array of 263 blocks,

and is divided into 4 Mbit banks. There are 31

banks each containing 8 main blocks of 32

KWords, and one parameter bank containing 8 pa-

rameter blocks of 4 KWords and 7 main blocks of

32 KWords. The Multiple Bank Architecture allows

Dual Operations, while programming or erasing in

one bank, Read operations are possible in other

banks. Only one bank at a time is allowed to be in

Program or Erase mode. It is possible to perform

burst reads that cross bank boundaries. The bank

architecture is summarized in Table 2, and the

memory maps are shown in Figure 4. The Param-

eter Blocks are located at the top of the memory

address space for the M58WR128ET, and at the

bottom for the M58WR128EB.

Each block can be erased separately. Erase can

be suspended, in order to perform program in any

other block, and then resumed. Program can be

suspended to read data in any other block and

then resumed. Each block can be programmed

and erased over 100,000 cycles using the supply

voltage VDD. There are two Enhanced Factory

programming commands available to speed up

programming.

Program and Erase commands are written to the

Command Interface of the memory. An internal

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified in the

Status Register. The command set required to

control the memory is consistent with JEDEC stan-

dards.

The device supports synchronous burst read and

asynchronous read from all blocks of the memory

array; at power-up the device is configured for

asynchronous read. In synchronous burst mode,

data is output on each clock cycle at frequencies

of up to 54MHz. The synchronous burst read oper-

ation can be suspended and resumed.

The device features an Automatic Standby mode.

When the bus is inactive during Asynchronous

Read operations, the device automatically switch-

es to the Automatic Standby mode. In this condi-

tion the power consumption is reduced to the

standby value IDD4 and the outputs are still driven.

The M58WR128E features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have

three levels of protection. They can be locked and

locked-down individually preventing any acciden-

tal programming or erasure. There is an additional

hardware protection against program and erase.

When VPP ≤ VPPLK all blocks are protected against

program or erase. All blocks are locked at Power-

Up.

The device includes a Protection Register and a

Security Block to increase the protection of a sys-

tem’s design. The Protection Register is divided

into two segments: a 64 bit segment containing a

unique device number written by ST, and a 128 bit

segment One-Time-Programmable (OTP) by the

user. The user programmable segment can be

permanently protected. The Security Block, pa-

rameter block 0, can be permanently protected by

the user. Figure 5, shows the Security Block and

Protection Register Memory Map.

The memory is available in a VFBGA60

12.5x12mm package and is supplied with all the

bits erased (set to ’1’).

7/87

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