LC75863E Просмотр технического описания (PDF) - SANYO -> Panasonic
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LC75863E Datasheet PDF : 24 Pages
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LC75863E, 75863W
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Recommended external resistance
Recommended external capacitance
Guaranteed oscillator range
Data setup time
Data hold time
CE wait time
ROSC
COSC
fOSC
tds
tdh
tcp
OSC
OSC
OSC
CL, DI
CL, DI
CE, CL
:Figure 2
:Figure 2
:Figure 2
39
1000
19
38
160
160
160
kΩ
pF
76 kHz
ns
ns
ns
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
Rise time
Fall time
DO output delay time
DO rise time
tcs
CE, CL
:Figure 2
tch
CE, CL
:Figure 2
tøH CL
:Figure 2
tøL CL
:Figure 2
tr
CE, CL, DI
:Figure 2
tf
CE, CL, DI
:Figure 2
tdc
DO RPU=4.7kΩ, CL=10pF *1 :Figure 2
tdr
DO RPU=4.7kΩ, CL=10pF *1 :Figure 2
160
160
160
160
160
160
ns
ns
ns
ns
ns
ns
1.5 µs
1.5 µs
Note: *1. Since DO is an open-drain output, these times depend on the values of the pull-up resistor RPU and the load capacitance CL.
Electrical Characteristics for the Allowable Operating Ranges
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Hysteresis
Power-down detection voltage
Input high level current
Input low level current
Input floating voltage
Pull-down resistance
Output off leakage current
Output high level voltage
Output low level voltage
Output middle level voltage *2
Oscillator frequency
Current drain
VH CE, CL, DI, KI1 to KI5
0.1 VDD
V
VDET
2.5
3.0
3.5 V
IIH
CE, CL, DI: VI = 6.0V
5.0 µA
IIL
CE, CL, DI: VI = 0V
–5.0
µA
VIF KI1 to KI5
0.05 VDD
V
RPD KI1 to KI5: VDD = 5.0V
50
100
250 kΩ
IOFFH DO: VO = 6.0V
6.0 µA
VOH1 KS1 to KS6: IO = –500µA
VLCD – 1.0 VLCD – 0.5 VLCD – 0.2
VOH2 P1 to P4: IO = –1mA
VLCD – 1.0
V
VOH3 S1 to S25: IO = –20µA
VLCD – 1.0
VOH4 COM1 to COM3: IO = –100µA
VLCD – 1.0
VOL1 KS1 to KS6: IO = 25µA
0.2
0.5
1.5
VOL2 P1 to P4: IO = 1mA
1.0
VOL3 S1 to S25: IO = 20µA
1.0 V
VOL4 COM1 to COM3: IO = 100µA
1.0
VOL5 DO: IO = 1mA
0.1
0.5
VMID1 COM1 to COM3: 1/2bias, IO = ±100µA
1/2VLCD – 1.0
1/2VLCD + 1.0
VMID2 S1 to S25: 1/3bias,IO = ±20µA
2/3VLCD – 1.0
2/3VLCD + 1.0
VMID3 S1 to S25: 1/3bias, IO = ±20µA
1/3VLCD – 1.0
1/3VLCD + 1.0
V
VMID4 COM1 to COM3: 1/3bias,IO = ±100µA
2/3VLCD – 1.0
2/3VLCD + 1.0
VMID5 COM1 to COM3: 1/3bias,IO = ±100µA
1/3VLCD – 1.0
1/3VLCD + 1.0
fosc OSC: ROSC = 39kΩ, COSC = 1000pF
30.4
38
45.6 kHz
IDD1 VDD :Sleep mode
100
IDD2 VDD: VDD = 6.0V, output open,fosc = 38kHz
270
540
ILCD1
ILCD2
VLCD : Sleep mode
VLCD: VLCD = 6.0V, output open, 1/2bias,
fosc = 38kHz
5
µA
100
200
ILCD3
VLCD: VLCD = 6.0V, output open, 1/3bias,
fosc = 38kHz
60
120
Note: *2. Excluding the bias voltage generation divider resistor built into VLCD1 and VLCD2. (See Figure 1.)
No. 7135-3/24
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