M58BF008ZA Просмотр технического описания (PDF) - STMicroelectronics

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M58BF008ZA

8 Mbit (256Kb x32, Burst) Flash Memory

STMicroelectronics 

M58BF008

System Clock (CLK). All synchronous signals

are input and output relative to the System Clock.

Synchronous input signals must respect the set-

up and hold times relative to the System Clock ris-

ing edge.

Reset/Power-down (RP). The Reset/Power-

down RP input provides a hardware reset for the

memory. When Reset/Power-down RP is at VIL

the memory is reset and in the Power-down mode.

In this mode the outputs are high impedance and

the current consumption is minimised. When Re-

set/Power-down RP is at VIH the memory is in the

normal operating mode. When leaving the Power-

down mode the memory enters the Asynchronous

Read Array mode.

Reset/Power-down has a weak pull-up resistor to

VDDQ and will assume a high level if not connect-

ed.

Chip Enable (E). When the Chip Enable E input

is at VIL it activates the memory control logic, input

buffers, decoders and sense amplifiers. When

Chip Enable E is at VIH the memory is deselected

and the power consumption is reduced to the

standby level.

Output Enable (G). Output Enable G controls the

data output buffers. In the Asynchronous mode

data is output when Output Enable G is at VIL. In

the Synchronous mode, Output Enable G is sam-

pled on the rising edge of the System Clock CLK.

If Output Enable E is at VIL then valid output data

on DQ0-DQ31 can be read at the next rising edge

of the System Clock CLK.

Output Disable (GD). In the Asynchronous

mode the data outputs DQ0-DQ31 are high imped-

ance when Output Disable GD is at VIL, irrespec-

tive of the state of Output Enable G. In

Synchronous mode Output Disable GD is sam-

pled, together with Output Enable G, on the rising

edge of the System Clock CLK. If Output Disable

is at VIL then the data outputs DQ0-DQ31 are high

impedance at the next rising edge of the System

Clock CLK, irrespective of the state of Output En-

able G.

Output Disable has a weak pull-up resistor to

VDDQ and will assume a high level if not externally

connected.

Write Enable (W). The Write Enable W input

controls the writing of commands or input data. In

the Asynchronous mode commands or data are

written when Chip Enable E and Write Enable W

are at VIL. In the Synchronous mode with Chip En-

able E at VIL, input data is sampled if Write Enable

W is at VIL on the rising edge of the System Clock

CLK.

Load Burst Address (LBA). In the Asynchro-

nous mode Load Burst Address LBA is Don’t Care

(but if it falls during an asynchronous read then a

new read cycle is started). In the Synchronous

mode Load Burst Address LBA enables latching of

the burst starting address for Synchronous read or

write. The address is latched on the rising edge of

the System Clock CLK if Load Burst Address LBA

is at VIL.

Write/Read (WR). Write/Read WR is used in

Synchronous mode to control write or read opera-

tions. If Load Burst Address LBA is at VIL and

Write/Read is at VIL then the rising edge of the

System Clock CLK latches a write address. If

Write/Read is at VIH then a read address is

latched.

Write/Read has a weak pull-up resistor to VDDQ

and will assume a high level if not externally con-

nected.

Burst Address Advance (BAA). When Burst

Address Advance BAA is at VIL, the rising edge of

the System Clock CLK advances the burst ad-

dress. When Burst Address Advance BAA is at VIH

the advance is suspended.

VDD Supply Voltage. The supply VDD provides

the power to the internal circuits of the memory.

The VDD supply voltage is 4.5 to 5.5V.

VDDQ Input/Output Supply Voltage. The Input/

Output supply VDDQ provides the power for the in-

put/outputs of the memory, independent from the

supply VDD. The Input/Output supply VDDQ may

be connected to the VDD supply or it can use a

separate supply of 3.0 to 3.6V.

VPP Program/Erase Supply Voltage. The Pro-

gram/Erase supply VPP is used for programming

and erase operations. The memory normally exe-

cutes program and erase operations at the supply

VPP1 voltage levels.

In a manufacturing environment, programming

may be speeded up by applying a higher VPPH lev-

el to the VPP Program/Erase Supply. This is not in-

tended for extended use. The VPPH supply may be

applied for a total of 80 hours maximum and during

program and erase for a maximum of 1000 cycles.

Stressing the device beyond these limits could

damage the device.

When VPP Program/Erase supply is at VSS all

blocks are protected from programming or erase.

Leaving VPP floating is equivalent to connecting it

to VSS due to an internal pull-down circuit.

Ground (VSS and VSSQ). The Ground VSS is the

reference for the internal supply voltage VDD. The

Ground VSSQ is the reference for the Input/Output

supply VDDQ.

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