M48Z512BV(2011) Просмотр технического описания (PDF) - STMicroelectronics
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M48Z512BV Datasheet PDF : 21 Pages
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M48Z512BV
3.3 V, 4 Mbit (512 K x 8 bit) ZEROPOWER® SRAM
Not recommended for new design
Features
■ Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■ Conventional SRAM operation; unlimited
) WRITE cycles
t(s ■ 10 years of data retention in the absence of
c power
du ■ Automatic power-fail chip deselect and WRITE
ro protection
P ■ 3.0 to 3.6 V operation
te – 2.9 V power-fail deselect
le ■ Pin and function compatible with JEDEC
o standard 512 K x 8 SRAMs
s ■ PMDIP32 is an ECOPACK® package
Ob ■ RoHS compliant
Obsolete Product(s) - – Lead-free second level interconnect
32
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PMDIP32 module
Description
The M48Z512BV ZEROPOWER® RAM is a non-
volatile, 4,194,304-bit static RAM organized as
524,288 words by 8 bits. The device combines an
internal lithium battery, a CMOS SRAM and a
control circuit in a plastic, 32-pin DIP module.
June 2011
Doc ID 14885 Rev 3
This is information on a product still in production but not recommended for new designs.
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