M48T559YMH1TR Просмотр технического описания (PDF) - STMicroelectronics
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M48T559YMH1TR Datasheet PDF : 18 Pages
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M48T559Y
Table 9. AC Characteristics
(TA = 0 to 70 °C; VCC = 4.5V to 5.5V)
Symbol
Parameter
tAS
tAH
tDS
tDH
tRLDV
tRLRH
tRHDZ
tWLWH
tELEH
tASLASH
tASHRL
tASHWL
tELRL
tEHDZ
tELWL
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Read Enable Access Time
R Pulse Width Low
Read Enable High to Output High Z
W Pulse Width Low
E Pulse Width Low
AS0, AS1 Pulse Width Low
AS0, AS1 High to R Low
AS0, AS1 High to W Low
Chip Enable Low to Read Enable Low
Chip Enable High to Data Output Hi-Z
Chip Enable Low to Write Enable Low
RAM OPERATION
Four control signals, AS0, AS1, R and W, are used
to access the M48T559Y. The address latches are
loaded from the address/data bus in response to
rising edge signals applied to the Address Strobe
0 (AS0) and Address Strobe 1 (AS1) signals. AS0
is used to latch the lower 8 bits of address, and
AS1 is used to latch the upper 5 bits of address.
It is not however necessary to follow any particular
order. The inputs are in parallel for the two ad-
dress bytes (upper and lower) and can be latched
in any order as long as the correct strobe is used.
It is necessary to meet the set-up and hold times
given in the AC specifications with valid address
information in order to properly latch the address.
If the upper and/or lower order addresses are cor-
rect from a prior cycle, it is not necessary to repeat
the address latching sequence.
A write operation requires valid data to be placed
on the bus (AD0-AD7), followed by the activation
of the Write Enable (W) line. Data on the bus will
be written to the RAM, provided that the write tim-
ing specifications are met. During a read cycle, the
Read Enable (R) signal is driven active. Data from
the RAM will become valid on the bus provided
that the RAM read access timing specifications are
met.
M48T559Y
Min
Max
20
0
60
0
70
70
25
50
50
15
15
15
0
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
The W and R signals should never be active at the
same time. In addition, E must be active before
any control line is recognized (except for AD0-AD7
and AS0, AS1).
RESET INPUT
The M48T559Y provides two debounced inputs
which can generate an output Reset. The duration
and function of the Reset output is identical to a
Reset generated by a power cycle. Pulses shorter
than tR1 and tR2 will not generate a Reset condi-
tion (see Table 12 and Figure 13).
DATA RETENTION MODE
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when VCC falls within the VPFD (max), VPFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as "don't care."
Note: A power failure during a write cycle may cor-
rupt data at the currently addressed location, but
does not jeopardize the rest of the RAM's content.
At voltages below VPFD (min), the user can be as-
sured the memory will be in a write protected state,
provided the VCC fall time is not less than tF.
6/18
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