M48T559 Просмотр технического описания (PDF) - STMicroelectronics

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M48T559

64 Kbit (8Kb x8) TIMEKEEPER® SRAM with ADDRESS/DATA MULTIPLEXED

STMicroelectronics 

Figure 3. Block Diagram

IRQ/FT

M48T559Y

32,768 Hz

CRYSTAL

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

16 x 8 BiPORT

SRAM ARRAY

POWER

8176 x 8

SRAM ARRAY

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

VPFD

W

DATA

R

TRANSCEIVER

UPPER

ADDRESS

LATCH

AD0-AD7

AS1

LOWER

ADDRESS

LATCH

AS0

RSTIN1

RST

VCC

RSTIN2

VSS

E

AI01676B

Table 3. Operating Modes (1)

Mode

VCC

E

R

Deselect

VIH

X

Write

Read

4.5V to 5.5V

VIL

VIH

VIL

VIL

Read

VIL

VIH

Deselect

VSO to VPFD (min) (2)

X

X

Deselect

≤ VSO

X

X

Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.

2. See Table 7 for details.

3. AD0-AD7, AS0, AS1 active when E is high and VCC > VPFD.

W

AD0-AD7

Power

X

High Z

VIL

DIN

VIH

DOUT

VIH

High Z

Standby (3)

Active

Active

Active

X

High Z

CMOS Standby

X

High Z Battery Back-up Mode

mation once per second. The information can be

accessed by the user in the same manner as any

other location in the static memory array.

The M48T559Y also has its own Power-fail Detect

circuit. The control circuitry constantly monitors

the single 5V supply for an out of tolerance condi-

tion.

When VCC is out of tolerance, the circuit write pro-

tects the SRAM, providing a high degree of data

security in the midst of unpredictable system oper-

ation brought on by low VCC. As VCC falls below

approximately 3V, the control circuitry connects

the battery which maintains data and clock opera-

tion until valid power returns.

3/18

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