M470L3223DT0-CB0 Просмотр технического описания (PDF) - Samsung
Номер в каталоге
Компоненты Описание
производитель
M470L3223DT0-CB0 Datasheet PDF : 16 Pages
| |||
M470L3223DT0
DDR SDRAM IDD spec table
Symbol
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
IDD0
720
640
IDD1
960
880
IDD2P
24
24
IDD2F
200
160
IDD2Q
160
144
IDD3P
280
240
IDD3N
440
360
IDD4R
1360
1120
IDD4W
1360
1120
IDD5
1440
1320
Normal
24
24
IDD6
Low power
12
12
IDD7A
2600
2240
A0(DDR200@CL=2)
600
800
24
144
128
200
320
960
920
1200
24
12
1880
Unit Notes
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA Optional
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
2. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR333(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. 0.0 Dec. 2001
Share Link: 