M2V56S20TP Просмотр технического описания (PDF) - Mitsumi

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производитель

M2V56S20TP

256M Synchronous DRAM

Mitsumi 

SDRAM (Rev.1.1)

Single Data Rate

Feb.2000

MITSUBISHI LSIs

M2V56S20/ 30/ 40/ TP -6, -7, -8

256M Synchronous DRAM

BLOCK DIAGRAM

DQ0-3 (x4), 0-7 (x8), 0 - 15 (x16)

I/O Buffer

Memory

Array

Bank #0

Memory

Array

Bank #1

Memory

Array

Bank #2

Memory

Array

Bank #3

Mode Register

Control Circuitry

Address Buffer

A0-12 BA0,1

Clock Buffer

Control Signal Buffer

CLK CKE /CS /RAS /CAS /WE DQMU/L

Type Designation Code

M 2 V 56 S 4 0

This rule is applied to only Synchronous DRAM family.

TP - 8

Speed Grade 6: 133MHz@CL3, 100MHz@CL2

7: 100MHz@CL2

8: 100MHz@CL3

Package Type TP: TSOP(II)

Process Generation

Function Reserved for Future Use

Organization 2n 2: x4, 3: x8, 4: x16

SDRAM Data Rate Type S:Single Data Rate

Density 56: 256M bits

Interface V:LVTTL

Memory Style (DRAM)

Mitsubishi Main Designation

MITSUBISHI ELECTRIC

3

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