M28C16-120K1TR Просмотр технического описания (PDF) - STMicroelectronics
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M28C16-120K1TR Datasheet PDF : 17 Pages
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M28C16B, M28C17B
Figure 4. Software Data Protection Enable Algorithm and Memory Write
Page Write
Timing
(see note 1)
Write AAh in
Address 555h
Write 55h in
Address 2AAh
Write A0h in
Address 555h
SDP is set
Page Write
Timing
(see note 1)
Physical
Page Write
Instruction
Write AAh in
Address 555h
Write 55h in
Address 2AAh
Write A0h in
Address 555h
Page Write
(1 up to 64 bytes)
Write
is Enabled
SDP Enable Algorithm
Write to Memory
When SDP is SET
AI02819
Note: 1. The most significant address bits (A10 to A6) differ during these specific Page Write operations.
ignored, and have no effect on the memory con-
tents.
The device remains in this mode until a valid Soft-
ware Data Protection disable sequence is re-
ceived. The device reverts to its “unprotected”
state.
The status of the Software Data Protection (en-
abled or disabled) is represented by a non-volatile
latch, and is remembered across periods of the
power being off.
The Software Data Protection Enable command
consists of the writing of three specific data bytes
to three specific memory locations (each location
being on a different page), as shown in Figure 4.
Similarly to disable the Software Data Protection,
the user has to write specific data bytes into six dif-
Figure 5. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
ferent locations, as shown in Figure 6. This com-
plex series of operations protects against the
chance of inadvertent enabling or disabling of the
Software Data Protection mechanism.
Figure 6. Software Data Protection Disable
Algorithm
Write AAh in
Address 555h
Write 55h in
Address 2AAh
Page Write
Timing
Write 80h in
Address 555h
Write AAh in
Address 555h
Write 55h in
Address 2AAh
DP
TB
PLTS
Hi-Z
= Data Polling
= Toggle Bit
= Page Load Timer Status
= High impedance
AI02815
Write 20h in
Address 555h
Unprotected State
AI02820
5/17
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