M28010 Просмотр технического описания (PDF) - STMicroelectronics
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M28010 Datasheet PDF : 23 Pages
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M28010
Read
The device is accessed like a static RAM. When E
and G are low, and W is high, the contents of the
addressed location are presented on the I/O pins.
Otherwise, when either G or E is high, the I/O pins
revert to their high impedance state.
Write
Write operations are initiated when both W and E
are low and G is high. The device supports both
W-controlled and E-controlled write cycles (as
shown in Figure 12 and Figure 13). The address is
latched during the falling edge of W or E (which
ever occurs later) and the data is latched on the
rising edge of W or E (which ever occurs first).
After a delay, tWLQ5H, that cannot be shorter than
the value specified in Table 9A to Table 9C, the
internal write cycle starts. It continues, under
internal timing control, until the write operation is
complete. The commencement of this period can
be detected by reading the Page Load Timer
Status on DQ5. The end of the internal write cycle
Figure 4. Software Data Protection Enable Algorithms (with or without Memory Write)
SDP is Disabled and Application
needs to Enable it, and Write Data
SDP is Disabled and
Application needs to Enable it
Page Write
Timing
Write AAh in
Address 5555h
Write 55h in
Address 2AAAh
Write A0h in
Address 5555h
Time Out (tWLQ5H)
Wait for write completion (tQ5HQ5X)
Page Write
Timing
Write AAh in
Address 5555h
Write 55h in
Address 2AAAh
Write A0h in
Address 5555h
Write data
in any addresses
within one page
Write
is enabled
SDP is set
Write AAh in
Address 5555h
Time Out (tWLQ5H)
Wait for write completion (tQ5HQ5X)
Page Write
Timing
Write 55h in
Address 2AAAh
Write A0h in
Address 5555h
Write data
in any addresses
within one page
Write
is enabled
DATA has been written
and SDP is Enabled
Time Out (tWLQ5H)
Wait for write completion (tQ5HQ5X)
DATA has been written
and SDP is Enabled
AI02227B
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