MT46V2M32 Просмотр технического описания (PDF) - Micron Technology
Номер в каталоге
Компоненты Описание
производитель
MT46V2M32 Datasheet PDF : 65 Pages
| |||
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached. The block is uniquely se-
lected by A1–Ai when the burst length is set to two, by
A2–Ai when the burst length is set to four and by A3–Ai
when the burst length is set to eight (where Ai is the
most significant column address bit for a given con-
figuration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.
BA0 BA1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register (Mx)
0* 0* Operating Mode CAS Latency BT Burst Length
* M13 and M12 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
M2 M1 M0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Length
M3 = 0
Reserved
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
Reserved
2
4
8
Reserved
Reserved
Reserved
Full Page
M3
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
000
001
010
011
100
101
110
111
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M11 M10 M9 M8 M7
00000
00010
-----
M6-M0
Valid
Valid
-
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
Figure 1
Mode Register Definition
64Mb: x32
DDR SDRAM
Table 1
Burst Definition
Burst
Length
2
4
8
Full
Page
(256)
Starting Column
Address
A0
0
1
A1 A0
00
01
10
11
A2 A1 A0
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
n = A0–A7,
A0 = 0
n = A0–A7,
A0 = 1
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
0-1
0-1
1-0
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn+1, Cn+2
Cn+3, Cn+4...
…Cn-1,
Cn…
Cn, Cn-1, Cn-2
Cn-3, Cn-4...
…Cn+1,
Cn…
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
Not supported
NOTE:
1. For a burst length of two, A1–A7 select the block
of two burst; A0 selects the starting column
within the block.
2. For a burst length of four, A2–A7 select the block
of four burst; A0–A1 select the starting column
within the block.
3. For a burst length of eight, A3–A7 select the block
of eight burst; A0–A2 select the starting column
within the block.
4. For a full-page burst, the full row is selected and
A0–A7 select the starting column. A0 also selects
the direction of the burst (incrementing if A0 = 0,
decrementing if A0 = 1).
5. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
Share Link: 