M66256FP Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC

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M66256FP

5120 × 8-BIT LINE MEMORY (FIFO)

MITSUBISHI ELECTRIC  

MITSUBISHI 〈DIGITAL ASSP〉

M66256FP

• N-bit del_a_y_2__ _____

(Sliding WRES and RRES at a cycle corresponding to delay length)

5120 × 8-BIT LINE MEMORY (FIFO)

Cycle 0 Cycle 1 Cycle 2 Cycle n–2 Cycle n–1 Cycle n Cycle n+1 Cycle n+2 Cycle n+3

WCK

RCK

tRESS tRESH

WRES

tRESS tRESH

RRES

tDS tDH

tDS tDH

Dn

(0)

(1)

(2)

(n–2)

(n–1)

(n)

(n+1)

(n+2)

(n+3)

m cycles

tAC

tOH

Qn

(0)

(1)

(2)

(3)

WE, RE = "L"

m ≥3

• N-bit delay_3_

(Disabling RE at a cycle corresponding to delay length)

Cycle 0 Cycle 1 Cycle 2

WCK

RCK

tRESS tRESH

WRES

RRES

RE

tDS tDH

Dn

(0)

(1)

(2)

HIGH-Z

Qn

m cycles

Cycle n–1 Cycle n Cycle n+1 Cycle n+2 Cycle n+3

tNREH tRES

tDS tDH

(n–2)

(n–1)

(n)

(n+1)

tAC

tOH

(0)

(1)

(n+2)

(2)

(n+3)

(3)

WE = “L”

m ≥3

9

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