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M29W512B

512 Kbit (64Kb x8, Bulk) Low Voltage Single Supply Flash Memory

STMicroelectronics 

M29W512B

STATUS REGISTER

Bus Read operations from any address always

read the Status Register during Program and

Erase operations.

The bits in the Status Register are summarized in

Table 6, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion. The Data Polling Bit is output on DQ7 when

the Status Register is read.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read operations from the ad-

dress just programmed output DQ7, not its com-

plement.

During Erase operations the Data Polling Bit out-

puts ’0’, the complement of the erased state of

DQ7. After successful completion of the Erase op-

eration the memory returns to Read Mode.

Figure 4, Data Polling Flowchart, gives an exam-

ple of how to use the Data Polling Bit. A Valid Ad-

dress is the address being programmed or any

address while erasing the chip.

Toggle Bit (DQ6). The Toggle Bit can be used to

identify whether the Program/Erase Controller has

successfully completed its operation. The Toggle

Bit is output on DQ6 when the Status Register is

read.

During Program and Erase operations the Toggle

Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-

sive Bus Read operations at any address. After

successful completion of the operation the memo-

ry returns to Read mode.

Figure 5, Data Toggle Flowchart, gives an exam-

ple of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Error Bit is set to ’1’ when a Pro-

gram or Chip Erase operation fails to write the cor-

rect data to the memory. If the Error Bit is set a

Read/Reset command must be issued before oth-

er commands are issued. The Error bit is output on

DQ5 when the Status Register is read.

Note that the Program command cannot change a

bit set at ’0’ back to ’1’ and attempting to do so may

or may not set DQ5 at ’1’. In both cases, a succes-

sive Bus Read operation will show the bit is still ’0’.

The Chip Erase command must be used to set all

the bits the memory from ’0’ to ’1’.

Table 6. Status Register Bits

Operation

Program

Program Error

Chip Erase

Erase Error

Note: Unspecified data bits should be ignored.

Address

Any Address

Any Address

Any Address

Any Address

DQ7

DQ7

DQ7

0

0

DQ6

Toggle

Toggle

Toggle

Toggle

DQ5

0

1

0

1

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