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M25P80-VMW3 Просмотр технического описания (PDF) - STMicroelectronics

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M25P80-VMW3 Datasheet PDF : 41 Pages
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M25P80
SPI MODES
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 6., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
Figure 5. Bus Master and Memory Devices on the SPI Bus
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SDO
SDI
SCK
CS3 CS2 CS1
CQD
CQD
CQD
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
S
W HOLD
S
W HOLD
S
W HOLD
Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 6. SPI Modes Supported
CPOL CPHA
0
0
C
1
1
C
D
Q
MSB
MSB
AI03746D
AI01438B
7/41

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